JPH05191224A - Synchronization circuit - Google Patents

Abstract

PURPOSE:To improve the high speed processing by making the operation of a high speed logic integrated circuit device including the synchronization circuit stable. CONSTITUTION:The synchronization circuit SYNC1 consists of a set/reset flip- flop SRF1 whose set input terminal S receives a substantial AND signal between an asynchronous input signal Sin and an inverse signal of a clock signal CK and whose reset input terminal R receives an inverse signal of the asynchronous input signal Sin and an inverse signal of the clock signal CK, and of an edge trigger flip-flop ETF1 whose data input terminal D receives an output signal n3 of the set/reset flip-flop SRF1 and operated synchronously with the leading edge of the clock signal CK.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit, for example, a synchronizing circuit included in a high-speed logic integrated circuit device and a technique particularly effective for stabilizing and speeding up its operation. It is a thing.

[0002]

2. Description of the Related Art There is a synchronizing circuit for synchronizing an asynchronous input signal which is formed asynchronously regardless of a clock signal with a clock signal and transmitting it to a subsequent circuit which operates synchronously according to the clock signal. There is a high-speed logic integrated circuit device to be mounted.

Regarding the synchronizing circuit, for example, 1979.
It is described in "Digital IC Practical Circuit Manual", page 114, etc. by Yojiro Yokoi, published by Radio Technology Co., Ltd.

[0004]

As the speed of high-speed logic integrated circuit devices and the like increases, the synchronizing circuit is mainly composed of edge-triggered flip-flops. For example, as shown in FIG. 4, an asynchronous input signal Sin is used. Edge-triggered flip-flop ETF2 and edge-triggered flip-flop ETF that take in according to the inverted signal of clock signal CK.
It also includes another edge-triggered flip-flop ETF3 that receives the second output signal n4 according to the non-inverted signal of the clock signal CK. As illustrated in FIG. 5, the asynchronous input signal Sin is synchronized with the falling edge of the clock signal CK and is edge-triggered flip-flop ETF2.
To the output signal n4, and further to the edge trigger type flip-flop ETF3 in synchronization with the rising edge of the clock signal CK to become its output signal, that is, the synchronous output signal Sout.

However, as the high-speed logic integrated circuit device and the like are further speeded up and the cycle of the clock signal is shortened, the following problems arise in the above-mentioned synchronizing circuit. Became clear by. That is, for example, as indicated by the thin line in FIG. 5, when the level of the asynchronous input signal Sin changes almost at the same time as the falling edge of the clock signal CK, the edge trigger flip-flop ETF2 is an edge trigger flip flop. Because of this, a so-called metastable state is produced, and the level of the output signal n4 is several tens of nanoseconds (10
It becomes unstable over a period Tm of ^-9 seconds). For this reason, when designing a system, the timing of metastable state must be set in consideration of the time until the metastable state settles, even though the probability of occurrence of the metastable state itself is extremely low. As a result, the speedup of the circuit device or the like is limited.

An object of the present invention is to provide a synchronizing circuit which shortens the period during which its output signal is in an unstable state and stabilizes and speeds up the operation. Another object of the present invention is to stabilize the operation of a high-speed logic integrated circuit device or the like including a synchronization circuit and promote its speeding up.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a synchronization circuit included in a high-speed logic integrated circuit device or the like has a set input terminal that receives a substantially logical product signal of a non-inverted signal of an asynchronous input signal and an inverted clock signal, and an asynchronous input signal at its reset input terminal. Of the set-reset flip-flop, and the data input terminal of the set-reset flip-flop whose output signal or asynchronous input signal and the set-reset flip-flop of the set-reset flip-flop An edge-trigger flip-flop that receives a logical AND signal with the output signal and that operates in synchronization with the rising edge of the clock signal.

[0009]

According to the above means, since the front-stage flip-flop of the synchronizing circuit can be a set-reset type flip-flop which does not generate the metastable state, the unstable state of the output signal of the synchronizing circuit can be shortened and the synchronizing signal can be reduced. It is possible to stabilize and speed up the operation of the activation circuit. as a result,
It is possible to stabilize the operation of a high-speed logic integrated circuit device or the like including a synchronization circuit and promote its speeding up.

[0010]

1 is a circuit diagram of a first embodiment of a synchronizing circuit to which the present invention is applied. Further, FIG. 2 shows a signal waveform diagram of an embodiment of the synchronizing circuit of FIG. Based on these figures, the outline and characteristics of the configuration and operation of the synchronization circuit SYNC1 of this embodiment will be described. The synchronization circuit SYNC1 of this embodiment is
Is included in a high speed logic integrated circuit device. Although not particularly limited, the circuit element of FIG. 1 is formed on one semiconductor substrate such as single crystal silicon together with other circuit elements (not shown) of the high speed logic integrated circuit device.

In FIG. 1, the synchronizing circuit SYNC1 is
The set reset flip-flop SRF1 receives the output signal n1 of the NAND gate NA1 at its set input terminal S and the output signal n2 of the NAND gate NA2 at its reset input terminal R, though not particularly limited thereto. An asynchronous input signal Sin from a pre-stage circuit (not shown) of the high-speed logic integrated circuit device is applied to one input terminal of the NAND gate NA1.
Is supplied to one input terminal of the NAND gate NA2, and an inverted signal from the inverter N1 is supplied to the input terminal.
An inverted signal (first clock signal) of the clock signal CK (second clock signal) by the inverter N2 is commonly supplied to the other input terminals of the NAND gates NA1 and NA2.

Here, as shown in FIG. 2, the clock signal CK is a pulse signal having a duty of about 50% which is repeatedly set to a high level or a low level in a predetermined cycle, and the asynchronous input signal Sin is a clock signal CK. Irrespective of that, it is set to a high level or a low level asynchronously. On the other hand, in the set-reset flip-flop SRF1, the input signal n1 supplied to the set input terminal S is set to the low level, in other words, the substantial logic of the asynchronous input signal Sin and the inverted signal of the clock signal CK. When the product signal is high level, it is in the set state,
By setting the input signal n2 supplied to the reset input terminal R to the low level, in other words, the substantial logical product signal of the inverted signal of the asynchronous input signal Sin and the inverted signal of the clock signal CK is set to the high level. By doing so, it is reset. The output signal n3 of the set-reset flip-flop SRF1 is set to the high level in the set state and set to the low level in the reset state.

The synchronizing circuit SYNC1 further includes an edge trigger type flip-flop ETF1 which receives the output signal n3 of the set / reset type flip-flop SRF1 at its data input terminal D. The clock signal CK is supplied to the clock input terminal CK of the edge trigger type flip-flop ETF1, and its output signal is the output signal of the synchronization circuit SYNC1, that is, the synchronization output signal Sou.
As t, it is supplied to a post-stage circuit (not shown) of the high-speed logic integrated circuit device. The edge trigger flip-flop ETF1 is not particularly limited, but the clock signal CK
Of the input signal n3 supplied to the data input terminal D is selectively set to a high level or a low level according to the logic level at the rising edge of the clock signal CK.

From these facts, the asynchronous input signal Sin
Is set to the low level, in the synchronizing circuit SYNC1, the output signal n1 of the NAND gate NA1 is fixed to the high level as shown in FIG.
Output signal n2 is selectively set to low level on condition that the clock signal CK is low level. For this reason,
In response to the first low level change of the output signal n2 of the NAND gate NA2, the set / reset type flip-flop SRF
1 is reset, and its output signal n3 is set to low level in synchronization with the falling edge of the clock signal CK. The low level of the output signal n3 is the clock signal CK.
Is taken into the edge-triggered flip-flop ETF1 at the first rising edge, and the output signal thereof, that is, the synchronous output signal Sout is brought to a low level.

Next, when the asynchronous input signal Sin is set to the high level, the output signal n2 of the NAND gate NA2 is fixed to the high level, and instead, the output signal n1 of the NAND gate NA1 is set to the low level as the clock signal CK. Is selectively set to low level. Therefore, the set / reset flip-flop SRF1 is set in response to the first change of the low level of the NAND gate NA1, and its output signal n3 is set to the high level in synchronization with the falling edge of the clock signal CK. The high level of the output signal n3 indicates that the edge trigger type flip-flop ETF1 is present at the first rising edge of the clock signal CK.
The output signal, that is, the synchronous output signal Sout is brought to a high level.

That is, the synchronizing circuit SYNC of this embodiment.
In 1, the set input terminal S and the reset input terminal R are
The output signal n1 of the NAND gate NA1 and the output signal n2 of the NAND gate NA2, which are supplied to, are complementarily formed according to the logic level of the asynchronous input signal Sin. Therefore, the set-reset flip-flop SRF1
Changes its state without generating a metastable state, and synchronizes the asynchronous input signal Sin with the low level of the clock signal CK and transmits it to the edge trigger type flip-flop ETF1. However, the operation of the synchronizing circuit SYNC1 is stabilized, and the period of the metastable state is substantially shortened, so that the period of the clock signal CK is correspondingly shortened.
It is possible to increase the speed by 1. As a result, the operation of the high-speed logic integrated circuit device including the synchronization circuit SYNC1 can be stabilized and its speed can be promoted.

FIG. 3 is a circuit diagram of a second embodiment of the synchronizing circuit to which the present invention is applied. Since the synchronizing circuit SYNC2 of this embodiment basically follows the synchronizing circuit SYNC1 of FIG. 1, only the parts different from this will be described.

In FIG. 3, the synchronizing circuit SYNC2 is
A NAND gate NA3 that receives the output signal n3 of the set-reset flip-flop SRF1 at its one input terminal
including. The asynchronous input signal Sin is supplied to the other input terminal of the NAND gate NA3, and its output signal is supplied to the data input terminal D of the edge trigger flip-flop ETF1 via the inverter N3.

That is, the synchronizing circuit SYNC of this embodiment.
2, the edge-triggered flip-flop ETF1
At the data input terminal D of the output signal n3 of the set-reset flip-flop SRF1.
And the edge-trigger flip-flop ETF1 outputs the asynchronous input signal Sin and the output signal n of the set-reset flip-flop SRF1.
When both 3 are at the high level, they are selectively set in response to the rising edge of the clock signal CK. However, even if pulsed noise is superimposed on the asynchronous input signal Sin while the clock signal CK is at the low level, the operation of the edge-triggered flip-flop ETF1 becomes relatively stable, which results in synchronization. The operation of the high-speed logic integrated circuit device including the synchronizing circuit SYNC2 and the synchronizing circuit SYNC2 is further stabilized.

As shown in the above two embodiments, the following effects can be obtained by applying the present invention to the synchronizing circuit included in the high speed logic integrated circuit device. That is, (1) the synchronization circuit included in the high-speed logic integrated circuit device is
The set input terminal receives a substantial logical product signal of the non-inverted signal of the asynchronous input signal and the inverted clock signal, and the reset input terminal receives a substantial logical product signal of the inverted signal of the asynchronous input signal and the inverted clock signal. A set-reset flip-flop to receive, and a data input terminal thereof receives a substantial logical product signal of the output signal of the set-reset flip-flop or the asynchronous input signal and the output signal of the set-reset flip-flop and receives the clock signal. An edge-triggered flip-flop that operates in synchronization with the rising edge makes the front-stage flip-flop of the synchronization circuit a set-reset flip-flop that does not generate a metastable state, and the output signal of the synchronization circuit becomes unstable. The effect that the state can be shortened is obtained. (2) According to the above item (1), it is possible to obtain the effect that the operation of the synchronizing circuit can be stabilized and speeded up. (3) According to the above items (1) and (2), it is possible to stabilize the operation of the high-speed logic integrated circuit device including the synchronization circuit and promote the speedup.

The invention made by the inventor of the present invention has been specifically described based on the embodiments, but the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIGS. 1 and 3, NAND gates NA1 and N
The A2, the inverter N2 and the like may be included in the set / reset type flip-flop SRF1.
Further, the edge-triggered flip-flop ETF1 may change its state at the falling edge of the clock signal CK, or the synchronization circuits SYNC1 and S.
It may be included in the subsequent circuit of YNC2. In FIG. 2, the phase relationship between the clock signal CK and the asynchronous input signal Sin, etc. is not restricted by this embodiment. Further, the first clock signal supplied to the set / reset type flip-flop SRF1 and the edge trigger type flip-flop ETF
The second clock signal supplied to 1 may be a separate clock signal. Further, the specific circuit configuration of the synchronization circuit in each example can take various embodiments as long as the logical conditions are the same.

In the above description, the case where the invention made by the present inventor is mainly applied to the synchronizing circuit included in the high-speed logic integrated circuit device which is the background field of application has been described, but the invention is not limited thereto. Not something
For example, the present invention can be applied to a single synchronization circuit or a similar synchronization circuit included in various digital integrated circuit devices. The present invention can be widely applied to at least a synchronizing circuit and a semiconductor device including the synchronizing circuit.

[0023]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a synchronization circuit included in a high-speed logic integrated circuit device or the like has a set input terminal that receives a substantially logical product signal of a non-inverted signal of an asynchronous input signal and an inverted clock signal, and an asynchronous input signal at its reset input terminal. Set-reset flip-flop that receives a substantial logical product signal of the inversion signal and the inverted clock signal, and the output signal of the set-reset flip-flop or the asynchronous input signal and the output of the set-reset flip-flop at its data input terminal. And an edge-triggered flip-flop that operates in synchronization with the rising edge of the clock signal. As a result, the front-stage flip-flop of the synchronization circuit can be a set-reset type flip-flop that does not generate the metastable state, so that the unstable state of the output signal of the synchronization circuit can be shortened and the operation of the synchronization circuit can be stabilized. It is possible to achieve higher speed and higher speed. As a result, it is possible to stabilize the operation of the high-speed logic integrated circuit device or the like including the synchronization circuit and promote the speed-up.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a synchronizing circuit to which the present invention is applied.

FIG. 2 is a signal waveform diagram showing an embodiment of the synchronization circuit of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of a synchronizing circuit to which the invention is applied.

FIG. 4 is a circuit diagram showing an example of a conventional synchronizing circuit.

5 is a signal waveform diagram showing an example of the synchronization circuit of FIG.

[Explanation of symbols]

SYNC1 to SYNC3 ... Synchronization circuit, SRF1.
... Set-reset flip-flops, ETF1 to ETF1
ETF3 ... Edge-triggered flip-flop, NA
1-NA3 ... NAND gate, N1-N4 ... Inverter. Sin ... Asynchronous input signal, CK ... Clock signal, Sout ... Synchronous output signal.

Claims (3)

[Claims] 1. A set input terminal receives a substantially logical product signal of a non-inverted signal of an asynchronous input signal and a first clock signal, and a reset input terminal thereof receives an inverted signal of the asynchronous input signal and a first clock signal. A set-reset type flip-flop whose output signal is supplied to a data input terminal of an edge-triggered flip-flop which operates according to a second clock signal. Synchronization circuit. 2. A set input terminal receives a substantially logical product signal of a non-inverted signal of an asynchronous input signal and a first clock signal, and a reset input terminal thereof receives an inverted signal of the asynchronous input signal and a first clock signal. A substantial logical product signal of the signal and a substantial logical product signal of its output signal and the asynchronous input signal is supplied to the data input terminal of the edge-triggered flip-flop that operates according to the second clock signal. A synchronization circuit including a set-reset flip-flop. 3. The first clock signal is an inverted signal of the second clock signal, and the edge-triggered flip-flop shifts its state in synchronization with a rising edge of the second clock signal. The synchronization circuit according to claim 1 or 2, wherein the synchronization circuit is one.