JP3230505B2 - Data transfer device for integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit data transfer method and apparatus, and more particularly to an integrated circuit data transfer method and apparatus for shortening a data transfer cycle.

[0002]

2. Description of the Related Art Referring to FIG. 6 (a) showing a block diagram of a main part of an example of a conventional data transfer apparatus of this kind,
A data output device 600 outputs data to be transferred from a data output terminal 604 via an output buffer 602 in response to a clock signal CLK supplied from outside and a D-type flip-flop circuit (hereinafter referred to as D-FF) 601. It is configured to be.

Referring to FIG. 6B which shows a timing chart for explaining the operation of the data transfer device, the internal delay time of the D-FF 601 with respect to the clock signal CLK is tq, and the output buffer for the output data of the D-FF 601. , The delay time tD of the transfer data is tq + tb.

That is, the data transfer cycle is set to Tcyc
le, assuming that the setup time of a data input device (not shown) to which the transfer data is supplied is ts, the data transfer cycle is limited by tD + ts.

As an example of improvement, a PLL (Phase L
There is an example using an "ocked Loop" circuit. Referring to FIG. 6C showing the block diagram and FIG. 6D showing the timing chart for explaining the operation thereof, the difference from the block diagram shown in FIG.
That is, the output signal of the PLL circuit 613 is supplied as the eleventh clock signal.

In this example, the internal delay time of the D-FF 611 with respect to the clock signal CLK is tq,
Assuming that the delay time of the output buffer 611 by the output buffer is tb and the time of the difference between the internal clock signal CLKi and the external clock signal CLK is tp, the delay time tD of the transfer data is tq + tb-tp.

That is, by advancing the internal clock signal CLKi by the time tp with respect to the external clock signal CLK, the delay time with respect to the external clock signal CLK becomes longer than the case of FIG. Also appears to be shorter by the time tp, so that the data transfer cycle is improved by the time tp.

[0008]

When the data transfer cycle is improved by using the PLL circuit in the above-mentioned conventional example, the PLL circuit itself keeps the output frequency until the output frequency is normally output with respect to the input frequency. During this period, an unstable state called a lock time is interposed. The time is a period of about 200 μSec to 1 mSec, but during this period, no external access is possible. In addition, since an unstable internal clock signal is generated during the lock time, the internal state of the data output device becomes unstable, and the internal state of the data output device is released after the lock time to release the unstable state. A reset cycle for resetting was required.

Further, there is a disadvantage that the chip area is increased due to the incorporation of the PLL circuit.

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above-mentioned drawbacks, and a high-speed data transfer is performed without using a PLL circuit in which the state of the device becomes unstable due to the lock time and the chip area becomes large. It is an object of the present invention to provide a data transfer method and device capable of performing the data transfer.

[0011]

According to the present invention, there is provided an integrated circuit data transfer device comprising: a first data output device having a first data output terminal and a first delayed clock output terminal;
A second data output device having a second data output terminal and a second delayed clock output terminal; a data input device having a data input terminal and a delayed clock input terminal; the first data output terminal; A data line connecting the data output terminal and the data input terminal to each other, and a delay clock line connecting the first delay clock output terminal, the second delay clock output terminal and the delay clock input terminal to each other. Wherein the first data output device latches data in synchronization with a clock signal and supplies the latched data to the first data output terminal; and a first data latch circuit which delays the clock signal and First clock delay means for supplying to the first delay clock output terminal, wherein the second data output device is synchronized with the clock signal. Latches the data and the second data latch circuit and supplies it to the second data output terminal,
Second clock delay means for delaying the clock signal and supplying the delayed clock signal to the second delayed clock output terminal, wherein the data input device receives the delay supplied from the delayed clock input terminal via the delayed clock wiring. A third data latch circuit that latches data supplied from the data input terminal via the data wiring in synchronization with a clock.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a block diagram showing a first embodiment of the data transfer device of the present invention, and FIG. 1B is a timing chart for explaining the operation. Referring to FIG. 1, a data output device 1
00 reads out data to be transferred by the D-FF 101 in synchronization with the external clock signal CLK supplied to the clock signal input terminal 104, and sends out the data to the data output line via the output buffer 102 and the output terminal 106;
The external clock signal CLK is delayed by the output buffer 103 and output to the clock output line as a delayed clock signal CLKd.

Here, D- with respect to clock signal CLK is
The internal delay time of the FF 101 is tq, and this D-FF 101
Assuming that the delay time of the output buffer 102 with respect to the output data is tb, the delay of the transfer data with respect to the external clock signal CLK is tq + tb. On the other hand, assuming that the time difference between the delayed clock signal CLKd and the external clock signal CLK is tb, the delay time tD of the transfer data with respect to the external clock signal CLK is tD = tq + tb-tb = tq.

That is, the transfer data delay time tD = t
q, which is substantially equivalent to advancing the internal clock signal by the time tq using the PLL circuit.

FIG. 2A shows an example of data transfer between the data output device 100 and the data input device 200, and FIG. 2 shows a timing chart for explaining the operation.
Referring to (b), the transfer data transmitted from the data output device 100 to the data transmission line is transmitted to the data input device 20.
The data is input to the D-FF 201 through the data input terminal 205 and is held in the D-FF 201 in synchronization with the delayed clock signal CLKd input through the clock signal input terminal 204. The transfer data held in the D-FF 201 is read into the next stage D-FF 202 in synchronization with an external clock signal supplied to the clock input terminal 203, and is taken out as reception data Di.

That is, the data input device 200 can use the delayed clock signal CLKd as an internal main clock. However, here, the data input device 200 uses an external clock signal CLK as a local clock signal for data transfer. An example of use is shown.

When the setup time of the data input device 200 is ts, the data transfer cycle is Tcycle, and the delay of the transfer data with respect to the clock signal CLK, that is, the delay time of the D-FF 101 and the output buffer 102 is tq + tb, the output buffer 103 delay time t
By setting B103 to tB103 = ts + tq + tb-Tcycle or more, data transfer in Tcycle becomes possible.

For example, if the delay time of the output buffer 103 is ts + tq + tb-Tcycle or more, the delay time tD with respect to the delay clock signal CLKd is tD = tq + tb- (ts + tq + tb-Tcycle).
e), and from this equation, tD + ts becomes tD + ts = tq + tb− (ts + tq + tb−Tcycle) + ts = Tcycle, and it can be seen that data transfer by Tcycle can be performed.

FIG. 3A is a block diagram showing an example of data transfer between two data output devices 300 and 310 and one data input device 200 as a second embodiment, and FIG. Referring to FIG. 3B showing a timing chart for description, the data output device 300 includes a D-FF 301 that reads data to be transferred in synchronization with an external clock signal CLK, and a data output device 300 in synchronization with the external clock signal CLK. A D-FF that reads a selection signal supplied through an input terminal 306 and outputs an enable signal
303 and the D-FF 30 in response to the enable signal.
1 output data buffer D1 for transmitting the transfer data output D1 to the data transmission line via the data output terminal 308, and the external clock signal CLK is delayed by a predetermined time to the clock transmission line via the output terminal 307. And an output buffer 304 for outputting.

The data output device 310 has the same configuration, and the components 301 and 311, 302 and 312, 303 and 313, 304 and 314, 305 and 315, 306 and 3
16, 307 and 317, 308 and 318, and the selection signal S
1 and S2 correspond to each other.

In these devices, data output devices are selected by selection signals S1 and S2, respectively. That is, taking the data output device 300 as an example, when the D-FF 303 latches the high level of the selection signal S1 at the falling timing of the external clock signal CLK and outputs the enable signal S1d to the output buffer 302, the output buffer 302 The state is activated, and the transfer data D1 of the D-FF 301 is transmitted to the data transmission line via the output buffer 302 and the output terminal 308.

At this time, the non-selected data output device 310
Is the D-FF 313 because the selection signal 2 is at the low level.
Becomes low, the output buffer 312 becomes inactive, the transmission of the transfer data is cut off, and the output goes into a high impedance state. However, since the transmission lines are pulled up by the terminating resistors on the data input device side, the data input device does not malfunction.

Next, when the selection signal S1 goes low and S2 goes high, the D-FF 313 latches this high level at the falling edge of the external clock signal CLK and outputs the enable signal S2d to the output buffer 312. Output buffer 312 is activated, and D
-The transfer data D2 of the FF 311 is transmitted to the data transmission line via the output buffer 312 and the output terminal 318. At this time, in the unselected data output device 300, since the selection signal S1 is at the low level, the output enable signal S1d of the D-FF 303 becomes low, the output buffer 302 becomes inactive and the transmission of transfer data is cut off. Its output goes into a high impedance state.

The feature of this configuration is that the data output device 300
Only outputs the delayed clock signal CLKd. However, on the mounting board, the data output device 3
The data output device 310 is designed so that the wiring delay of the data signal 00 and the delayed clock signal CLKd becomes equal.
To the data input device 200 and the data output device 300
When the wiring delay amount is Δt, the wiring delay time of only the data transmitted from the data output device 310 differs by Δt, and the data arrives later by that amount. Therefore, the delayed clock signal CL
The delay of the transfer data with respect to Kd is tD + Δt,
The data transfer cycle will be limited by tD + Δt + ts.

Such a situation may actually occur because the transfer data and the delayed clock signal are output from the same data output device so that the delay times are easily equalized.

FIG. 4A is a block diagram showing an example of data transfer in which a selected data output device outputs a delayed clock signal CLKd according to a third embodiment in order to solve the problem, and its operation. Referring to FIG. 4B showing a timing chart for explanation, the data output device 400 includes a D-FF 401 that reads data to be transferred in synchronization with an external clock signal CLK, and a data output device 400 in synchronization with the external clock signal CLK. A D-FF 403 that reads the selection signal S1 supplied via the input terminal 407 and outputs an enable signal S1d, and transfers the transfer data output D1 of the D-FF 401 via the data output terminal 308 in response to the enable signal S1d. An output buffer 402 with an enable function for transmitting to a transmission line, and an external clock signal CLK
A D-FF 404 that reads the enable signal S1d in synchronization with the clock signal and outputs an enable signal S1c; And an output buffer 405 for outputting.

The data output device 410 has the same configuration, and the components 401 and 411, 402 and 412, 403 and 413, 404 and 414, 405 and 415, and 406 and 4
16, 407 and 417, 408 and 418, and the selection signal S
1 and S2 correspond to each other.

In this case, delayed clock signal CLKd is output only when one of data output devices 400 and 410 is selected. In other words, since the data output device having this configuration outputs the transfer data and the latch timing signal of the data together, the data output device 400 and the data of the data output devices 400 and 410 and the wiring delay time of the delayed clock signal CLKd Are designed to be equal to each other, so that the delay difference Δ
Solved the delay of t.

The value required to make the above wiring delay times equal is the data delay tD. It is assumed that the data output device outputs the difference between the delay clock CLKd and the transfer data on the data transmission line while maintaining the value of the delay tD. Also, if the delay amount of the delay clock CLKd and the delay amount of the transfer data on the subsequent transmission line are different from each other, the value of the delay tD changes in the data input device by the difference. Therefore, the delay amount of the delay clock CLKd on the transmission line must be equal to the delay amount of the transfer data. Although there is no problem if the wiring delay amounts of the data output devices 400 and 410 are different from each other, the delay amount of the delay clock CLKd and the delay amount of the transfer data in each data output device need to be equal.

It should be noted that the delayed clock signal CLKd performs a clock operation only when it is selected, which contributes to a reduction in power consumption.

Here, the D-FF and the output buffer applied to the apparatus of each embodiment described above will be described. Referring to FIGS. 5A to 5C which are circuit diagrams of the D-FF and the output buffer, these circuits are generally used well-known circuits. The D-FF has a data input terminal D connected to a latch circuit composed of inverters 302a and 302b via a transfer gate N1, and an output terminal of the latch circuit connected to a transfer gate N2.
, And the output terminal of the latch circuit is connected to the output terminal Q so as to output the same polarity as the input data. A clock terminal C is connected to a gate electrode of the transfer gate N1 via an inverter 302f, and an output terminal of the inverter 302f is connected to a gate electrode of the transfer gate N2 via an inverter 302c. Data is latched at the rising timing of the external clock signal CLK, and data is output at the falling timing of the next clock signal.

This type of D-FF is shown in FIGS.
In FIGS. 3A, 3A, 4A, 6A and 6C, a clock input terminal is marked with a circle.

On the other hand, D-FFs having no clock symbol at their clock input terminals, that is, D-FFs 404 and 414 in FIG. 4A, latch data at the rising edge of an external clock signal and output the next clock signal. Data is output at the rising timing.
2f is deleted, and the clock terminal C is directly connected to the gate of the transfer gate N1 and the input terminal of the inverter 302C.

The output buffer shown in FIG.
N is connected to the gate electrode of an open-drain-connected N-channel MOS transistor N3 via an inverter 303a. The input signals are output in phase.

The output buffer with an enable function shown in FIG. 5C has an input terminal IN connected to one input terminal of a two-input NAND 405a, an enable terminal E connected to the other input terminal, and an output terminal of the NAND 405a having an open drain. It is connected to the gate electrode of the connected N-channel MOS transistor N4. When the enable terminal is at a high level, the input signals are output in phase.

[0036]

As described above, the data transfer method and device for an integrated circuit of the present invention output transfer data in synchronization with an external clock signal by a data output device.
The clock generation means delays and outputs the external clock signal by a time equal to the data delay amount in the data output device, and transfers the transfer data transferred from the data output device in synchronization with the delayed clock signal output from the clock generation means. A data transfer method for receiving the delayed clock-synchronized output data into a data input side in synchronization with an external clock signal by a data input device, and a data output device for synchronizing with an externally supplied clock signal. Data output means for outputting predetermined data, and clock delay means for delaying and outputting an external clock signal by a time equal to the data delay amount of the data output means. A stage before receiving transfer data in synchronization with the delay clock signal and its delay clock Because it has a data transfer apparatus comprising data input means and a rear stage to take the synchronization of transmitted data further in synchronization with the clock signal, substantially PL
The speed is increased as if the internal clock signal was advanced by a predetermined time using the L circuit.

[Brief description of the drawings]

FIG. 1A is a block diagram illustrating a data transfer device according to a first embodiment of the present invention. (B) A timing chart for explaining the operation.

2A is a block diagram showing an example of data transfer between a data output device 100 and a data input device 200. FIG.
(B) A timing chart for explaining the operation.

FIG. 3A is a block diagram showing an example of data transfer between two data output devices 300 and 310 and one data input device 200 as a second embodiment.

FIG. 4A is a block diagram showing an example of data transfer between two data output devices 400 and 410 and one data input device 200 as a third embodiment. (B) A timing chart for explaining the operation.

FIG. 5A is a circuit diagram of a D-FF. (B) It is a circuit diagram of an output buffer. FIG. 3C is a circuit diagram of an output buffer with an enable function.

FIG. 6A is a block diagram of a conventional data output device. (B) A timing chart for explaining the operation. (C) is a block diagram of another conventional data output device using a PLL circuit. (D) is a timing chart for explaining the operation.

[Explanation of symbols]

100, 300, 400 Data output device 101, 201, 202, 203, 301, 303, 3
11,313,401,403,404,411,41
3,414 D-FF 102,103,304,313 Output buffer 302,312,402,405,412,415
Output buffer with enable function N1, N2 Transfer gate N3, N4 N-channel MOS transistor 405a 2-input NAND

Claims (6)

(57) [Claims] A first data output device having a first data output terminal and a first delayed clock output terminal;
A second data output device having a data output terminal and a second delayed clock output terminal; a data input device having a data input terminal and a delayed clock input terminal;
A data line for interconnecting the data output terminal, the second data output terminal, and the data input terminal, and the first delay clock output terminal, the second delay clock output terminal, and the delay clock input terminal. A first data latch circuit, comprising: a delay clock line connected to each other; wherein the first data output device latches data in synchronization with a clock signal and supplies the latched data to the first data output terminal; First clock delay means for delaying a clock signal and supplying the same to the first delay clock output terminal, wherein the second data output device latches data in synchronization with the clock signal and A second data latch circuit for supplying the second data output terminal; and a clock signal for delaying the clock signal and supplying the delayed clock signal to the second delay clock output terminal. A second clock delay means, wherein the data input device is supplied from the data input terminal via the data wiring in synchronization with a delayed clock supplied from the delayed clock input terminal via the delayed clock wiring. An integrated circuit data transfer device comprising a third data latch circuit for latching data. 2. The data input device further includes a fourth data latch circuit that receives the data latched by the third data latch circuit and latches the data in synchronization with the clock signal. An integrated circuit data transfer device according to claim 1. 3. The first and second data output devices,
3. The integrated circuit data transfer device according to claim 1, further comprising: means for setting the first and second data output terminals to a high impedance state in response to the non-selection state. 4. The first and second data output devices,
In response to the non-selection state, the first
And means for setting the second delay clock output terminal to a high impedance state.
A data transfer device for an integrated circuit as described in the above. 5. The first and second data latch circuits respectively latch corresponding data in synchronization with one edge of the clock signal and supply the latched data to the first and second data output terminals, respectively. A first selection signal latch circuit for latching a first selection signal in synchronization with the one edge of the clock signal, and a second edge of the clock signal. A second selection signal latch circuit that latches the selection signal latched by the first selection signal latch circuit in synchronization with
Means for setting the first data output terminal to a high impedance state based on the selection signal latched by the first selection signal latch circuit, and the second circuit based on the selection signal latched by the second selection signal latch circuit Means for setting one delayed clock output terminal to a high impedance state, wherein the second data output device latches a second selection signal in synchronization with the one edge of the clock signal. A selection signal latch circuit, a fourth selection signal latch circuit for latching the selection signal latched by the third selection signal latch circuit in synchronization with the other edge of the clock signal, and the third selection signal Means for setting the second data output terminal to a high impedance state based on the selection signal latched by the latch circuit; and the fourth selection signal latch circuit Claim, characterized by further comprising a means for a high impedance state the second delayed clock output terminal based on the latched selection signal 1
Or the data transfer device for an integrated circuit according to 2. 6. equal to said first generally data transfer cycle the sum of the setup time delay difference time and the data input device of the clock signal from the data output first delayed clock output terminal from the data output terminal The data transfer device according to claim 1, wherein: