KR100303996B1 - Multiphase Detection Device - Google Patents

Abstract

The present invention relates to a multi-phase detection device that detects a phase difference between an external clock and an internal clock in the early stage of DLL operation and transfers the information to the DLL circuit to reduce the locking time. A pre-phase detection means for detecting a phase difference between the internal clock and the internal clock in advance, and a clock selection signal is initialized to select a corresponding clock source from among a plurality of clock sources preset by the detection signal from the pre-phase detection means. By providing the initial clock selection control means for delay compensation from the source, the phase difference between the external clock and the internal clock is detected in advance at the beginning of the DLL operation, and the clock source that is initially initialized is selected. Will be reached.

Description

Multiphase Detection Device

The present invention relates to a multiphase detection device, and more particularly, to a multiphase detection device configured to detect a phase difference between an external clock and an internal clock at the beginning of a DLL operation.

The DLL (Delay Locked Loop) is a clock recovery circuit used to accurately synchronize the phase of the internal clock with the external clock of the chip. The DLL is delayed and synchronized with the phase of the external clock. Since the phase difference between the internal clock and the external clock is not known at the beginning of operation, the DLL circuit should be able to give a maximum phase delay of 360 °.

For example, the locking time of a DLL in Direct Rambus DRAM is as follows.

Fig. 1 is a conventional phase diagram in which clk0 to clk315 are clock sources having a phase difference of 0 ° to 315 °, and an internal clock is produced by this clock source.

At the beginning of DLL operation, it is reset to clk0, and it moves by unit delay every 11 cycles in the clockwise or counterclockwise direction of the diagram according to the phase of the initial internal clock until the phase of the external clock and the internal clock are the same. Done.

In this case, when the locking time is long, the delay must be compensated by the phase of 180 °. 64 unit delay is required to compensate for 45 ° phase delay, 256 unit delay is required to compensate for 180 ° phase delay, and one unit delay moves every 11 clock cycles, so the maximum locking time is 2816 clock cycles. need. This requires a locking time of 7.04μs when using a 400MHz clock.

Accordingly, the present invention has been made in view of the above-described conventional situation, and a multi-phase detection device for detecting a phase difference between an external clock and an internal clock in the early stage of DLL operation and transferring the information to the DLL circuit to reduce the locking time. The purpose is to provide.

In order to achieve the above object, a multiphase detection apparatus according to a preferred embodiment of the present invention includes pre-phase detection means for detecting a phase difference between an external clock and an internal clock before operation of a delay locked loop;

An initial clock selection control means for initializing a clock selection signal to select a corresponding clock source among a plurality of clock sources preset by the detection signal from the pre-phase detection means, and for performing delay compensation from the selected clock source; It is characterized by.

1 is a conventional phase diagram,

2 is a block diagram of a multi-phase detection device according to an embodiment of the present invention;

3 is an internal configuration diagram of the pre-phase detection means shown in FIG.

4 is an internal configuration diagram of an initial clock selection control means shown in FIG.

5 is a waveform diagram illustrating the operation of the pre-phase detection means according to an embodiment of the present invention.

<Description of the reference numerals for the main parts of the drawings>

10: pre-phase detection means 20: initial clock selection control means

22: transfer unit 24: clock select signal initialization unit

12-18: D flip flop

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a multi-phase detection device according to an embodiment of the present invention, which includes a pre-phase detection means 10 for detecting a phase difference between an external clock and an internal clock before a DLL (delay locked loop) operation. Initial clock selection control means 20 for controlling the clock source to be initially selected by the detection signal output from the pre-phase detection means 10.

The pre-phase detection means 10 is composed of four rising edge triggered D flip flops 12-18, as shown in Fig. 3, each of the D flip flops 12-18. At the rising edges of the input clocks clk0, clk45, clk90, and clk135, the "low / high" state of the internal clock int.clk is output as the respective output signals out0, out45, out90, and out135. For example, if the internal clock (int. Clk) is low when clock 0 (clk0) transitions from low to high, the Q output of the D flip-flop 12 becomes low and the output signal out0 becomes low level. Becomes

In this way, the pre-phase detection means 10 detects the phase difference between the external clock and the internal clock int. Clk with four output signals out0, out45, out90, and out135.

In Fig. 3, reference numerals clk0, clk45, clk90, and clk135 are internally generated clocks.

The initial clock selection control means 20 transmits the clock selection signals po0, pe0, po1, pe1 to the output signals out0, out45, out90, of the pre-phase detection means 10 during the reset period. depending on the state of out135), a number of circuits for initializing " low / high "

4 is a circuit for generating a clock selection signal po0 among the clock selection signals po0, pe0, po1, pe1 of the initial clock selection control means 20. During the reset period, the pre-phase detection means 10 While transmitting the signal from out0 to the clock selection signal initialization unit 24 at the rear stage, when the normal operation after reset, the external control signal (D) is input to the clock selection signal initialization unit 24 at the rear stage. And a clock selection signal initialization section 24 composed of a D flip-flop that initializes the reset section clock selection signal po0 by the signal from the transmission section 22.

The transfer unit 22 includes a NAND gate serving as a first logic operation element 30 for NAND processing a reset signal Reset and a signal out0 from the prephase detection means 10; A second logical operation for receiving a signal out0 from the pre-phase detection means 10 and a reset signal / Reset inverted by the inverter IV connected to the node r and performing NOR processing; An output element 36 for outputting a predetermined signal to the clock selection signal initialization section 24 by the NOR gate as the element 32 and the signals from the first and second logical operation elements 30 and 32; And a transfer gate 34 which transfers an external control signal D to the clock selection signal initialization unit 24 based on the reset signal Reset and the inverted reset signal / Reset.

The output element 36 is connected between a power supply voltage terminal and an output terminal K to perform on / off switching operation by a signal from the first logical operation element 30 and the output terminal K. And an NMOS transistor (N) connected between the ground terminal and the ground voltage terminal and performing on / off switching operation by a signal from the second logical operation device (32).

In the initial clock selection control means 20 configured as described above, in the case of the po0 output, if the signal out0 from the prephase detection means 10 is "high" during the reset period, the po0 is initialized to "high", If the signal out0 from the prephase detecting means 10 is " low ", po0 is initialized to " low ". When the normal operation is performed after the reset, po0 becomes the external control signal (D).

In the embodiment of the present invention, the clock selection signals po0, pe0, po1, pe1 output from the initial clock selection control means 20 are transmitted to a phase multiplexer circuit (not shown), and the clock selection signals po0, The clock sources selected according to pe0, po1 and pe1) are shown in Table 1 below.

po0 po1 Clock source pe0 pe1 Clock source 0 0 clk225 0 0 clk180 0 One clk315 0 One clk270 One 0 clk135 One 0 clk90 One One clk45 One One clk0

In the multi-phase detection device according to the embodiment of the present invention configured as described above, signals (out0, out45, out90, out135) detected by the pre-phase detection means 10 are present at the rear end of the initial clock selection control means 20. Table 2 below shows the relationship of converting the information to the phase multiplexer circuit (not shown).

out0 out45 out90 out135 First selected clock source po0 pe0 po1 pe1 One One One One clk0 to clk45 One One One One One One One 0 clk45-clk90 One One One 0 One One 0 0 clk90-clk135 One One 0 0 One 0 0 0 clk135-clk180 One 0 0 0 0 0 0 0 clk180-clk225 0 0 0 0 0 0 0 One clk225-clk270 0 0 0 One 0 0 One One clk270 to clk315 0 0 One One 0 One One One clk315 to clk0 0 One One One

In Table 2 above, if the signals out0, out45, out90, and out135 output from the prephase detection means 10 are "11", the internal clock (int. Clk) must be delayed between 270 DEG and 315 DEG. The clock sources to be initialized are clock 270 and clock 315 because they can be in phase with the clock, and the clock selection signals to be initialized are po0 = "L", po1 = "H", pe0 = "L", pe1 = "H "to be.

In the case of other conditions, the clock selection signals po0, pe0, po1, pe1 are initialized by the same method.

5 is a waveform diagram illustrating an example of an operation of a multiphase detection apparatus according to an exemplary embodiment of the present invention.

clk0, clk45, clk90, and clk135 are internally created clocks. clk0 is a clock with no phase difference compared to an external clock. clk45 is a clock with a 45 ° phase difference compared to an external clock. , clk90 is a clock with a phase difference of 90 ° compared to an external clock, and clk135 is a clock with a phase difference of 135 ° compared to an external clock.

As shown in the figure, when the phase difference between the external clock and the initial internal clock (int. Clk) is between 135 ° and 180 °, the external clock and the initial internal clock (int. Clk) are actually in the same phase relationship. The interval to be delayed is between 180 ° and 225 °.

Therefore, the signals out0, out45, out90, and out135 output from the prephase detection means 10 become " 0 ". That is, since the initial internal clock is low when clk0 transitions from low to high, the output signal out0 of the prephase detection means 10 becomes "0", and the initial internal clock when clk45 transitions from low to high. Since the clock is in the low state, the output signal out45 of the prephase detecting means 10 becomes "0". When the clk90 transitions from low to high, the initial internal clock is in the low state. The output signal of out90 is " 0 ", and since the initial internal clock is low when clk135 transitions from low to high, the output signal out135 of the prephase detection means 10 becomes " 0 ".

Accordingly, the clock selection signals po0, pe0, po1, pe1 output from the initial clock selection control means 20 are initialized to " 0 " to start the DLL operation with an internal clock delayed by 180 °.

According to the present invention as described above, the locking point can be reached with a unit delay movement of up to 45 DEG by selecting a clock source which is initially initialized by detecting the phase difference between the external clock and the internal clock in advance at the beginning of the DLL operation.

This can implement a DLL having a significantly faster locking time at a quarter level of the conventional Direct Rambus DRAM DLL locking time.

On the other hand, the present invention is not limited only to the above-described embodiments, but may be modified and modified without departing from the scope of the present invention.

Claims (8)

Pre-phase detecting means for detecting in advance a phase difference between the external clock and the internal clock before operation of the delay locked loop; An initial clock selection control means for initializing a clock selection signal to select a corresponding clock source among a plurality of clock sources preset by the detection signal from the pre-phase detection means, and for performing delay compensation from the selected clock source; Multi-phase detection device, characterized in that. The multiphase detection apparatus according to claim 1, wherein the prephase detection means comprises a plurality of D flip flops configured to detect a phase difference between an external clock and an internal clock in a predetermined number of sections. 2. The apparatus of claim 1, wherein the initial clock selection control means comprises a transfer unit for transmitting a signal from the pre-phase detection unit to a reset section and an external control signal after reset, and a signal from the transfer unit. And a plurality of circuits comprising a clock selection signal initialization unit for initializing a clock selection signal in a reset section. 4. The apparatus of claim 3, wherein the transfer unit is configured to receive a logic operation by receiving the reset signal and the signal from the pre-phase detection unit, and a reset signal inverted from the signal from the pre-phase detection unit. A second logical operation element which is received and logically operated, an output element which outputs a predetermined signal to the clock selection signal initialization unit by signals from the first and second logical operation elements, and an inverted signal from the reset signal And a transfer gate for transmitting an external control signal to the clock selection signal initialization unit by a set signal. 5. The multi-phase detection device according to claim 4, wherein the first logical operation element is composed of two input NAND gates. 5. The multi-phase detection device according to claim 4, wherein the second logical operation element is composed of two input NOR gates. 5. The PMOS transistor of claim 4, wherein the output element comprises a PMOS transistor that is turned on / off by a signal from the first logical operation element and an NMOS transistor that is turned on or off by a signal from the second logic operation element. Multi-phase detection device, characterized in that consisting of. 4. The multi-phase detection device according to claim 3, wherein the clock select signal initialization unit comprises a D flip flop.