KR980006517A - Semiconductor structure and fabrication process with reduced back transfer capacitance - Google Patents

Abstract

The present invention relates to a structure and a manufacturing process of a power MOSF ET having reduced reverse transmission capacitance in a semiconductor manufacturing process.

The constitution of the present invention includes an N-type epitaxial layer formed by growing a high purity silicon layer on an N-type substrate; A gate oxide film formed by oxidizing an upper portion of the epitaxial layer; Polysilicon is formed on the gate oxide film, and the portion is not formed by the etching process, the polysilicon is etched with the gate oxide film and separated into two parts; A high concentration P-type body under both of the upper part of the epitaxial layer and the etched polysilicon and gate oxide region; A low-concentration P-type body positioned on the side portions of the high-concentration P-type body, both lower portions of the gate oxide film, and under the etched polysilicon and gate oxide region to form a P-type well together with the high-concentration P-type body; A high concentration N-type source formed by injecting high concentration N-type impurities into both P-type wells to form a channel; PSG formed by depositing on top of the two separated polysilicon and the exposed high concentration N-type source; It is formed by depositing on top of the PSG, the exposed high concentration P-type body, and consists of a metal connecting two separate high concentration N-type sources.

The effects of the present invention can provide a MOSFET structure and a manufacturing process that reduce Crss, which can improve switching characteristics by etching the lower portion of the polysilicon and the gate oxide film where no channel is formed, thereby lowering the overall Crss.

Description

Semiconductor structure and fabrication process with reduced back transfer capacitance

As this is a public information case, the full text was not included.

3 is a plan view of a power MOSFET with reduced reverse transfer capacitance according to an embodiment of the present invention.

Claims (6)

A MOSFET comprising: an N-type epitaxial layer formed by growing a high purity silicon layer on an N-type substrate; A gate oxide film formed by oxidizing an upper portion of the epitaxial layer; Polysilicon formed on the gate oxide layer and selectively etched together with the gate oxide layer to form a portion where a channel is not formed by an etching process; It is formed through the injection and diffusion of high concentration P-type impurities in both the upper part of the epitaxial layer and the lower portion of the etched polysilicon and the gate oxide layer region, the upper side of the high concentration P-type body, both of the gate oxide film A low concentration P-type body disposed under the etched polysilicon and gate oxide region to form a P type well with a high concentration P-type body; A high concentration P-type body in both of said P-type wells to form a channel; A high concentration N-type source formed by injecting high concentration N-type impurities into both P-type wells to form a channel; PSG formed by depositing on top of the two separated polysilicon and the exposed high concentration N-type source; And a metal structure formed by depositing the upper portion of the PSG and the exposed high concentration P-type body and connecting two separated high-concentration N-type sources. The semiconductor structure according to claim 1, wherein the high concentration P-type body formed below the selective etched region and the N-type epitaxial layer form a junction to operate as a P-N diode. The semiconductor structure according to claim 1, wherein the high concentration P-type body formed under the selective etched region and the N-type epitaxial layer form a junction to operate as a P-N diode. Forming an N-type epitaxial layer of the same type on the N-type substrate, growing a gate oxide film thereon, and depositing polysilicon on top of the gate oxide film; Selectively etching polysilicon together with the gate oxide layer, wherein the gate oxide layer and polysilicon are also etched together in a region where the channel is not formed, and forming a P type well by depositing a high concentration P type body and a low concentration P type body. Wow; Implanting high concentration N-type impurities to form a high concentration N-type source to form a junction; Depositing a PSG on top of the unetched polysilicon and an exposed low concentration P-type body, and forming a source portion by depositing a metal on top of the PSG and an exposed high concentration P-type body; A semiconductor manufacturing process with reduced reverse transfer capacitance characterized in that the. The semiconductor manufacturing process according to claim 4, wherein the high concentration P-type body formed under the selective etched region and the N-type epitaxial layer form a junction to operate as a PN diode. . The semiconductor manufacturing process according to claim 4, wherein the high concentration P-type body formed under the selective etched region and the N-type epitaxial layer form a junction to operate as a PN diode. .