KR100194681B1 - Semiconductor structure and manufacturing process with reduced reverse transfer capacitance - Google Patents

Abstract

The present invention relates to a structure and a manufacturing process of a power MOSFET in which a reverse transfer capacitance is reduced in a semiconductor manufacturing process.

An N-type epitaxial layer is formed by growing a high-purity silicon layer on an N-type substrate. A gate oxide film formed by oxidizing an upper portion of the epitaxial layer; Polysilicon formed on the gate oxide film and separated into two parts by etching the gate oxide film with a portion where no channel is formed by the etching process; A high concentration P-type body under both the upper portion of the epitaxial layer and the etched polysilicon and the gate oxide region; A low-concentration P-type body located at the side of the high-concentration P-type body, both sides of the gate oxide film, and under the etched polysilicon and the gate oxide region to form the P-type well together with the high-concentration P-type body; A high-concentration N-type source formed by implanting high-concentration N-type impurities into both of the P-type wells to form a channel; A PSG formed by depositing on top of two separated polysilicon and on top of an exposed high-concentration N-type source; The upper part of the PSG is formed by depositing on the exposed high-concentration P-type body, and is made of a metal connecting two separated high-concentration N-type sources.

The effect of the present invention is to provide a MOSFET structure and a fabrication process in which C _rss , which can improve the switching characteristics, is reduced by etching the lower portion of the polysilicon and the gate oxide film where no channel is formed and lowering the entire C _rss .

Description

Semiconductor structure and manufacturing process with reduced reverse transfer capacitance

FIG. 1 is a plan view of a power MOSFET according to a conventional technique,

FIG. 2 is a vertical structure view of a conventional power MOSFET,

FIG. 3 is a plan view of a power MOSFET having a reduced reverse transfer capacitance according to an embodiment of the present invention,

FIG. 4 is a vertical structure view of a power MOSFET in which a reverse transfer capacitance is reduced according to an embodiment of the present invention,

FIGS. 5 (a) to 5 (e) illustrate a fabrication process of a power MOSFET having a reduced reverse transfer capacitance according to an embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

10: N-type substrate 20: epitaxial layer

30: high-concentration P-type body 40: low-concentration P-type body

50: high-concentration N-type source 60: gate oxide (gate oxide)

70: Polysilicon 80: Phosphosilicate (PSG)

90: Metal

This invention is that a semiconductor structure and the manufacturing process reduces the reverse transfer capacitance, especially reverse transfer capacitance in the semiconductor manufacturing process (Reverse Transfer Capacitance: below C _rss) in which metal reducing-oxide-semiconductor field effect transistor (Metal-Oxide -Semiconductor Field Effect Transistor: hereinafter referred to as MOSFET).

Hereinafter, a conventional power MOSFET will be described with reference to the accompanying drawings.

FIG. 1 is a plan view of a power MOSFET according to a conventional technique,

FIG. 2 is a vertical structure view of a power MOSFET according to a conventional technique.

Referring to FIG. 2, in the conventional power MOSFET,

An N-type epitaxial layer 20 formed by growing a high-purity silicon layer having an appropriate thickness so that a dopant concentration is uniformly distributed through a high-concentration N-type substrate 10; A gate oxide 60 formed by oxidizing the upper portion of the epitaxial layer 20; Polycrystalline silicon is deposited on the gate oxide layer 60 and the gate oxide layer 60 is etched to form a polysilicon layer located at the center of the upper portion of the epitaxial layer 20 70); A high concentration P type body (P ⁺ body) 30 formed on both sides of the epitaxial layer 20 through injection and diffusion of high concentration P type impurities; Type body 30 and the gate oxide film 60. The P-type body 30 is formed by implanting and diffusing a low-concentration P-type impurity and is located at both the upper side of the high-concentration P- A low concentration P type body (P ^- body) 40 forming a well; A high-concentration n-type source (N ⁺ source) 50 formed by implanting high-concentration n-type impurities into both the p-type wells; A phosphosilicate (hereinafter referred to as PSG) 80 formed by depositing on top of the polysilicon 70 and the exposed high-concentration n-type source 50; And a metal 90 formed on the upper portion of the PSG 80 and on the exposed upper portion of the P-type body 30 by vapor deposition.

The operation of the conventional power MOSFET according to the above configuration is as follows.

FIG. 1 is a plan view of a power MOSFET, which is made up of a rectangular or square active cell, and the vertical structure of the section AB is shown in FIG.

Referring to FIG. 2, a conventional power MOSFET is formed by growing a high-purity silicon layer of an appropriate thickness so as to uniformly distribute a dopant concentration through a high-concentration n-type substrate 10 to form an n-type epitaxial layer 20, And the upper part of the epitaxial layer 20 is oxidized to form a gate oxide film 60. Polysilicon 70 is formed by depositing polycrystalline silicon on the gate oxide film 60, And is located at the upper central portion of the epitaxial layer 20 by the etching process together with the gate oxide film 60.

Then, the high-concentration P-type body 30 is formed by injecting and diffusing the high-concentration P-type impurity into both sides of the epitaxial layer 20, and then the low-concentration P-type body 30 Type body 40 and the low concentration P-type body 40 are positioned on the upper side of the high-concentration P-type body 30 and on both sides of the gate oxide film 60, Thereby forming a well.

Then, a high-concentration N-type source 50 is formed by implanting high-concentration N-type impurities into both of the P-type wells. Then, an upper portion of the polysilicon 70 and an upper portion of the exposed high- Type body 30. The PSG 80 is formed on the PSG 80 and is deposited on the exposed high-concentration P-type body 30 to form a metal 90.

In the structure of the power vertical MOSFET product using the rectangular and square active cells of FIG. 1, the reverse transfer capacitance (C _rss ) of the polysilicon portion and the gate oxide film formed by the P-type body 30, . That is, C _rss

C _rss = C _gd C _ox × A _g

C _gd is the gate-channel capacitance, C _ox is the capacitance of the oxide film per unit area, and A _g is the area of the gate oxide film. At this time, C _rss is also generated in the portion where the channel is not formed in the lower part of the active cells.

However, the conventional power MOSFET uses a rectangular and square active cell. The increase in the C _rss due to the remaining polysilicon portion and the gate oxide film, in which the P-type body junction is generated, In the case of driving, there is a problem in that the switching surface is inferior.

Therefore capable object of this invention is intended to solve the above problems, by etching the lower portion of the polysilicon and gate oxide film that is the channel is not formed, reducing the gate area, improving the switching characteristics by decreasing the total C _rss C _rss And to provide a MOSFET structure and manufacturing process that reduces the size of the MOSFET.

As a means for achieving the above object,

An N-type epitaxial layer formed by growing a high-purity silicon layer on an N-type substrate;

A gate oxide film formed by oxidizing the upper portion of the epitaxial layer;

Polysilicon formed on the gate oxide film and separated into two portions by etching the portion where the channel is not formed by the etching process together with the gate oxide film;

A high-concentration P-type body formed by implanting and diffusing high-concentration P-type impurities into both the upper portion of the epitaxial layer and the etched polysilicon and the gate oxide film region;

Type P-type body, both sides of the gate oxide film, and under the etched polysilicon and the gate oxide film region, so that the high-concentration P-type body is formed by implanting and diffusing low-concentration P- A low-concentration P-type body forming a P-type well together with the low concentration P-type body;

A high-concentration N-type source formed by implanting high-concentration N-type impurities into both of the P-type wells to form a channel;

A PSG formed by depositing an upper portion of the separated two polysilicon layers and an upper portion of the exposed high-concentration N-type source;

The upper part of the PSG is formed by depositing on the exposed high-concentration P-type body, and is formed of a metal connecting two separated high-concentration N-type sources.

Further, as another means for attaining the above object,

Forming an N type epitaxial layer of the same type on an N type substrate, growing a gate oxide film thereon, and depositing polysilicon on the gate oxide film;

The polysilicon is selectively etched together with the gate oxide film. At this time, the area of the gate oxide film is reduced by etching the gate oxide film and the polysilicon located at the portion where no channel is formed, and a high concentration P type body and a low concentration P type body Depositing a P-type well to form a P-type well;

Implanting a high-concentration N-type impurity to form a junction to form a high-concentration N-type source;

Depositing a PSG on top of the un-etched polysilicon and exposed low-concentration P-type body;

And forming a source portion by depositing a metal on an upper portion of the PSG and an upper portion of the exposed high-concentration P-type body.

The most preferred embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a plan view of a power MOSFET having a reduced C _rss according to an embodiment of the present invention,

FIG. 4 is a vertical structure view of a power MOSFET having a reduced C _rss according to an embodiment of the present invention,

5 (a) to 5 (e) illustrate a manufacturing process of a power MOSFET having a reduced C _rss according to an embodiment of the present invention.

As shown in FIG. 4, the configuration of a power MOSFET having a reduced C _rss according to an embodiment of the present invention,

An N-type epitaxial layer 20 formed by growing a high-purity silicon layer of an appropriate thickness so as to uniformly distribute the dopant concentration through the high-concentration N-type substrate 10;

A gate oxide film 60 formed by oxidizing the upper portion of the epitaxial layer 20;

Polysilicon 70 is formed by depositing polycrystalline silicon on the gate oxide film 60 and etched together with the gate oxide film 60 by a part where no channel is formed by the etching process. ;

A high-concentration P-type body 30 formed on both sides of the epitaxial layer 20 and below the etched polysilicon and the gate oxide film region through injection and diffusion of high-concentration P-type impurities;

Concentration p-type impurity is injected and diffused, and the upper side of the high-concentration P-type body 30, the lower both sides of the gate oxide film 60, and the upper part of the etched polysilicon 70, Type body 40 which is located under the region of the high-concentration P-type body 60 and forms a P-type well together with the high-concentration P-type body 30;

A high-concentration N-type source 50 formed by implanting high-concentration N-type impurities into both of the P-type wells to form a channel;

A PSG 80 formed by depositing an upper portion of the separated two polysilicon 70 and an upper portion of the exposed high-concentration N-type source 50;

The upper portion of the PSG 80 is formed on the exposed upper portion of the P-type body 30 and the metal 90 is formed by depositing the two highly concentrated N-type sources 50.

As shown in FIGS. 5 (a) to 5 (e), a manufacturing process of a power MOSFET having a reduced C _rss according to an embodiment of the present invention,

The N type epitaxial layer 20 of the same type is formed on the high concentration N type substrate 10 and the gate oxide film 60 is grown thereon and the polysilicon 70 is deposited on the gate oxide film 60 (Step 5a);

The polysilicon 70 is selectively etched together with the gate oxide film 60. At this time, the gate oxide film 60 and the polysilicon 70 located at the portions where no channel is formed are also etched, (30b) and the low concentration P-type body (30) to form a P-type well (FIG. 5b);

Implanting a high-concentration N-type impurity to form a junction to form a high-concentration N-type source 50 (FIG. 5c);

Depositing a PSG 80 on top of the un-etched polysilicon 70 and exposed low-concentration P-type body 40 (FIG. 5d);

And forming a source portion by depositing a metal on the upper portion of the PSG 80 and the upper portion of the exposed high-concentration P-type body 30 (FIG. 5e).

The operation of the power MOSFET having a reduced C _rss according to the embodiment of the present invention with the above configuration is as follows.

In the MOS transistor for power switch, unnecessary excess polysilicon and gate oxide film generated in the structure of the rectangular and square active cells are selectively removed.

In other words, conventionally, since the switching speed of the device is reduced due to the increase of C _{rss at} the time of V _DS low-voltage _driving , the area of the gate oxide film can be reduced by etching as shown in Equation (1) , That is, by selectively etching the polysilicon and the gate oxide film in which the P-type well region is not formed, a junction by the P-type bodies 30 and 40 is generated in the active region from which the polysilicon is removed, Since the PN junction diode is formed together with the gate electrode 20, it is possible to improve the switching characteristic by inducing a fast current of the vertical current.

Referring to FIG. 4, a power MOSFET having a reduced reverse transfer capacitance is formed by growing a high-purity silicon layer having an appropriate thickness so as to uniformly distribute the dopant concentration through the high-concentration N-type substrate 10 to form an N-type epitaxial layer 20 , And the upper portion of the epitaxial layer 20 is oxidized to form a gate oxide film 60. [

Next, a polycrystalline (70) cone is formed on the gate oxide film 60, and the portion where the channel is not formed is etched together with the gate oxide film 60 by the etching process to separate into two parts .

Then, the high-concentration P-type body 30 is formed by injecting and diffusing the high-concentration P-type impurity into both the upper portion of the epitaxial layer 20 and the upper portion of the etched polysilicon and the gate oxide film region, Type body 40 is formed through the injection and diffusion of the gate oxide film 60. The upper side of the high-concentration P-type body 30, the lower both sides of the gate oxide film 60, and the etched polysilicon 70 And the gate oxide film 60 and forms a P-type well together with the high-concentration P-type body 30. 5 (a), a N type epitaxial layer 20 of the same type is formed on a high concentration N type substrate 10, a gate oxide film 60 is grown thereon, and a gate oxide film The polysilicon 70 is selectively deposited on the polysilicon layer 60 together with the gate oxide layer 60 with reference to FIG. 5 (b) Type well 30 and the low-concentration P-type body 30 are deposited to form a P-type well. The gate oxide film 60 and the polysilicon 70 are also etched together with the high-concentration P-type body 30 and the low-

Next, high-concentration N-type impurities are implanted into both of the P-type wells to form a channel of the MOSFET to form a high-concentration N-type source 50. Then, the upper portion of the two separated polysilicon 70 and the exposed high concentration Type source 50 to form a PSG 80. The metal 90 is formed on the upper portion of the PSG 80 and on the exposed upper portion of the P-type body 30, And the two high concentration N-type sources 50 are connected. 5 (c), a high-concentration N-type source 50 is formed by implanting a high-concentration N-type impurity to form a junction. Referring to FIG. 5 (d) The PSG 80 is deposited on the upper portion of the exposed polysilicon 70 and the exposed lower concentration P-type body 40. Referring to FIG. 5 Type body 30. The source is formed by depositing a metal on the high-concentration P-type body 30.

As a result, as shown in FIG. 3, the active regions of the rectangular and square active cells have the same cross-section as A'B 'by selectively removing polysilicon 70 and gate oxide 60, 60) can be reduced to lower the C _rss , and a PN diode is formed in the portion where the polysilicon is removed, so that the vertical current can be rapidly induced to improve the switching characteristic.

Therefore, the effect of the present invention, which operates as described above, is to reduce the C _rss that can improve the switching characteristics by lowering the entire C _rss by etching the lower part of the channel oxide and the lower part of the gate oxide film, .

Claims (6)

1. A MOSFET comprising: an N-type epitaxial layer formed by growing a high-purity silicon layer on an N-type substrate; A gate oxide film formed by oxidizing the upper portion of the epitaxial layer; Polysilicon formed on the gate oxide film and separated into two portions by etching the portion where the channel is not formed by the etching process together with the gate oxide film; A high-concentration P-type body formed by implanting and diffusing high-concentration P-type impurities into both the upper portion of the epitaxial layer and the etched polysilicon and the gate oxide film region; Type P-type body, both sides of the gate oxide film, and under the etched polysilicon and the gate oxide film region, so that the high-concentration P-type body is formed by implanting and diffusing low-concentration P- A low-concentration P-type body forming a P-type well together with the low concentration P-type body; A high-concentration N-type source formed by implanting high-concentration N-type impurities into both of the P-type wells to form a channel; A PSG formed by depositing an upper portion of the separated two polysilicon layers and an upper portion of the exposed high-concentration N-type source; And a metal layer formed on the upper portion of the PSG and formed on the exposed upper portion of the P-type body to connect the two separated N-type high concentration sources. The semiconductor structure according to claim 1, wherein the high-concentration P-type body formed under the selectively etched region and the N-type epitaxial layer are bonded to form a P-N diode. 2. The semiconductor structure of claim 1, wherein the low-concentration P-type body and the N-type epitaxial layer formed under the selective etched region are bonded to form a P-N diode. Forming an N type epitaxial layer of the same type on an N type substrate, growing a gate oxide film thereon, and depositing polysilicon on the gate oxide film; The polysilicon is selectively etched together with the gate oxide film. At this time, the gate oxide film and the polysilicon, which are located at the portions where the channel is not formed, are also etched, and the P type well and the low concentration P type body are deposited to form the P type well ; Implanting a high-concentration N-type impurity to form a junction to form a high-concentration N-type source; Depositing PSG on top of the unexposed polysilicon and exposed low-concentration P-type body; Forming a source region by depositing metal on top of the PSG and on top of the exposed high concentration P-type body. ≪ Desc / Clms Page number 20 > 5. The semiconductor device according to claim 4, wherein the high-concentration P-type body and the N-type epitaxial layer formed below the selective etching region are bonded to form a PN diode. . 5. The semiconductor device according to claim 4, wherein the low-concentration P-type body and the N-type epitaxial layer formed under the selective etching region are bonded to form a PN diode. .