JPH0695535B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a junction field effect transistor having a diode built in between a source and a drain.

[Conventional technology]

Conventionally, in order to protect a semiconductor device from surge power, a diode for absorbing surge is often externally attached, and even in the case of a junction field effect transistor (called J-FET), the equivalent circuit diagram of FIG. As shown in, the diode d is externally attached or built in between the source S and the drain D.

FIG. 2 is a sectional view of a conventional diode built-in type J-FET. In the figure, 1 is a P-conductivity type gate substrate, 2 is an N-conductivity type channel layer formed on the gate substrate 1, 3
Is a P-conductivity type gate region formed inside the channel layer 2, and 4 and 5 are a source region and a drain region provided in the channel layer 2 with the gate region 3 interposed therebetween. An N-channel J-FET section is constituted by the above elements. Thus, a part of the channel layer 2 has a cathode region 6 of the built-in diode portion which is separated in an island shape by a P-conductivity type separation layer reaching from the surface to the gate substrate layer. Type anode region 8 '
Are formed. A conductive connection is established between the source electrode S and the anode region 8 ′ and between the drain electrode D and the cathode region 6, and a gate electrode G is formed from both the substrate gate 1 and the upper gate region 3. Has been withdrawn.

[Problems to be solved by the invention]

J-FET with conventional built-in diode described above
, The gate region 3 and the diode anode region 8 '
Were formed at the same time and had the same diffusion junction depth.
Therefore, there are the following problems.

In the case of the J-FET, the channel thickness d shown in FIG. 2 is usually as thin as 2 μ or less. In the diode portion of FIG. 2, a PNP transistor is parasitically formed between the anode region 8 ′, the cathode region 6 and the gate substrate 1, and particularly when the d channel thickness is thin, it easily operates as a PNP transistor, There was a possibility of causing unintended operation. Moreover, when a reverse voltage is applied to the PN diode to cause breakdown, an unintended current flows between the source and the gate.

[Means for solving problems]

In the semiconductor device of the present invention, a channel region of opposite conductivity type is formed in a substrate of one conductivity type to be a gate region, and the one conductivity type gate region having a high impurity concentration and the gate region are provided in the channel region. A junction-type field effect transistor having a high impurity concentration reverse conductivity type drain and a source region, respectively, and a single conductivity type substrate provided independently of the reverse conductivity type channel region. A first region of the opposite conductivity type; a second region of the opposite conductivity type having a high impurity concentration, which is connected to the drain region provided in an island shape in the first region; And a third region of one conductivity type that is provided in an island shape and is connected to the source region, and is formed shallower than the junction depth of the gate region of the transistor.

〔Example〕

 Next, the present invention will be described with reference to examples.

FIG. 1 is a sectional view of an embodiment of the present invention. In FIG. 1, comparing this with the conventional example of FIG. 2, the J-FET portion composed of the substrate gate 1, the channel layer 2, the gate region 3, and the source / drain regions 4 and 5 is the same. However,
In the built-in diode portion provided between the source and the drain of the J-FET, a high concentration N conductivity type region 7 is formed in an N conductivity type cathode region 6 separated in an island shape.
In the conductivity type region 7, a high concentration P conductivity type anode region 8 having a shallower diffusion depth than the gate region 3 of the J-FET portion is formed.

By making the anode region 8 shallower than the gate region 3 in this way, the distance d ′ between the diode junction and the bottom of the cathode region 6 becomes wider, and the PNP parasitic composed of the anode region 8, the cadence region 6 and the substrate gate layer 1 is formed. Since the base width of the transistor is widened, the parasitic transistor operation is less likely to occur. In addition, since the impurity concentration of the base region of the parasitic transistor is set to be high, the lifetime of a small number of carriers is shortened, which makes the parasitic transistor operation more difficult to occur.

In the above embodiment, one conductivity type is the P conductivity type and the opposite conductivity type is the N conductivity type.
N channel J-FET with built-in conductivity type diode
However, the present invention is also applicable to a P-channel J-FET having a built-in diode, in which the P conductivity type is changed to the N conductivity type and the N conductivity type is changed to the P conductivity type in the above embodiment. Needless to say.

〔The invention's effect〕

As described above, according to the present invention, in the case of the N-channel J-FET, the transistor operation of the parasitic PNP transistor is increased by increasing the concentration of the cathode region of the diode and decreasing the diffusion depth of the anode region. Is less likely to occur, a stable P-N junction diode is formed between D and S, and a J-FET in which malfunction does not easily occur can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 3 is an equivalent circuit diagram of a JFET having a built-in diode, and FIG. 2 is a sectional view of a conventional semiconductor device. 1 ... P-type substrate gate, 2 ... N-type channel layer, 3 ...
P-type gate region, 4,5 ... N ⁺ source / drain region, 6
...... N type cathode area, 7 ...... N ⁺ cathode area, 8 ......
P ₊ anode region, S ... source electrode, D ... drain electrode, G ... gate electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 29/812

Claims (1)

[Claims] 1. A channel region of opposite conductivity type is formed in a substrate of one conductivity type to be a gate region, and the gate region of one conductivity type having a high impurity concentration and the gate region are sandwiched in the channel region. And a junction field effect transistor formed by respectively forming a high impurity concentration reverse conductivity type drain and a source region, and the reverse conductivity type channel region provided independently in the one conductivity type substrate. Reverse conductivity type first
Region, the second region of the opposite conductivity type having a high impurity concentration connected to the drain region provided in the first region in an island shape, and the island region provided in the second region. And a third region of the one conductivity type which is connected to the source region and is formed shallower than a junction depth of the gate region of the transistor.