KR980006435A - 불휘발성 반도체 메모리 - Google Patents
불휘발성 반도체 메모리 Download PDFInfo
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- KR980006435A KR980006435A KR1019970023328A KR19970023328A KR980006435A KR 980006435 A KR980006435 A KR 980006435A KR 1019970023328 A KR1019970023328 A KR 1019970023328A KR 19970023328 A KR19970023328 A KR 19970023328A KR 980006435 A KR980006435 A KR 980006435A
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- Prior art keywords
- gate electrode
- insulating film
- floating gate
- semiconductor memory
- gate insulating
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- 239000004065 semiconductor Substances 0.000 title claims 17
- 239000013078 crystal Substances 0.000 claims abstract 2
- 239000000969 carrier Substances 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 2
- 239000013081 microcrystal Substances 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 239000002784 hot electron Substances 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
- G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/561—Multilevel memory cell aspects
- G11C2211/5612—Multilevel memory cell with more than one floating gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
Abstract
데이터의 개서 가능 횟수가 많은 다치 메모리를 제공한다. 단결정 실리콘 기판(1)상의 소스·드래인 영역(2)사이의 채널 영역(3)상에 게이트 산화막(4)과, 부유 게이트 전극(5)과, 게이트 산화막(6)과, 제1 제어 게이트 전극(7)과, 게이트 산화막(8), 제2 제어 게이트 전극(9)과, 절연막(10)이 형성되어 있다. 부유 게이트 전극(5)은 게이트 산화막(4)에 대해 수직 방향으로 늘어난 기둥모양의 도전성 미세 결정(주상정)으로 이루어지고, 그 각 주상정은 서로 절연되어 있다. 기입 동작에서는, 드래인 영역(2b)에서 늘어나는 공핍층의 폭을 제어하여 부유 게이트 전극(5)으로 열전자를 주입하는 것으로 다치의 각 데이터값에 대응하여 부유 게이트 전극(5)의 소정 부분에 소정량의 전자를 축적시킨다. 그리고, 판독 동작에서는, 공핍층의 폭을 제어하고, 또 각 제어 게이트 전극(7,9)의 전위를 제어하는 것으로 다치의 각 데이터값에 대응한 셀 전류를 얻는다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 제1 실시 형태의 제조 방법을 설명하시 위한 개략 단면도.
제3도는 제1 실시 형태의 제조방법을 설명하기 위한 개략 사시도.
제4도는 제1 실시 형태의 제조방법을 설명하기 위한 개략 단면도.
제5도는 제1 실시 형태의 동작을 설명하기 위한 설명도.
Claims (9)
- 부유 게이트 전극(5)을 분할한 각 부분(5a, 5b)에 반송자를 축적시켜 다치의 데이터값을 기억시키는 것을 특징으로 하는 불휘발성 반도체 메모리.
- 반도체층(1)에 형성된 채널 영역(3)상에 게이트 절연막(4)을 사이에 두고 부유 게이트 전극(5)이 형성되고, 그 게이트 절연막을 통하지 않는 부유 게이트 전극을 분할한 각 부분(5a, 5b)으로 에너지를 낮게 제어한 열 반송자를 주입하며, 그 각 부분마다 독립하여 반송자를 축적시키는 것으로 각 부분마다 다른 데이터를 기억시키는 것을 특징으로 하는 불휘발성 반도체 메모리.
- 제2항에 있어서, 공핍층(12)의 폭을 제어함으로써, 부유 게이트 전극의 소정 부분만 열 반송자를 주입하는 것을 특징으로 하는 불휘발성 반도체 메모리.
- 제2항 또는 제3항에 있어서, 공핍층(12)의 폭을 제어하고, 제어 게이트 전극 (7,9)의 전위를 제어함으로써, 다치의 각 데이터값에 대응한 셀 전류를 얻는 것을 특징으로 하는 불휘발성 반도체 메모리.
- 제1항 내지 제4항의 어느 한항에 있어서, 반도체층(1)에 형성된 채널 영역(3)상에 제1 게이트 절연막(4)과, 부유 게이트 전극(5)과, 제2 게이트 절연막( 6)과, 제1 제어 게이트 전극(7)과, 제3 게이트 절연막(8)과, 제2 제어 게이트 전극 (9)이 이 순서로 적층되고, 제1 및 제2 제어 게이트 전극의 전위를 반도체층의 전위에 대해 임의로 설정함으로써, 제1 제어 게이트 전극으로부터 제2 게이트 절연막을 통해 부유 게이트 전극으로 열 발송자를 주입하는 것을 특징으로 하는 불휘발성 반도체 메모리.
- 제1항 내지 제4항의 어느 한항에 있어서, 반도체층(1)에 형성된 채널 영역(3)상에 제1 게이트 절연막(4)과, 부유 게이트 전극(5)과, 제2 게이트 절연막( 6)과, 반도체 게이트 전극(7)과, 금속 게이트 전극(13)이 이 순서로 적층되고, 금속 게이트 전극 및 반도체 게이트 전극의 전위를 반도체층의 전위에 대해 임의로 설정하는 것으로, 반도체 게이트 전극으로부터 제2 게이트 절연막을 통해 부유 게이트 전극으로 열 발송자를 주입하는 것을 특징으로 하는 불휘발성 반도체 메모리.
- 제5항 또는 제6항에 있어서, 부유 게이트 전극(5)은 제1 게이트 절연막(4)에 대해 수직 방향으로 연장하는 기둥 모양의 도전성 미세 결정으로 이루어지고, 그 각미세 결정은 인접하는 미세 결정과 전기적으로 절연되어 있는 것을 특징으로 하는 불휘발성 반도체 메모리.
- 제1항 내지 제7항의 어느 한항에 있어서, 1도전형의 열 반송자를 부유 게이트 전극(5)으로 주입하는 것으로 데이터의 기입을 행하고, 데이터의 기입시와는 반대인 도전형인 열 반송자를 부유 게이트 전극으로 주입함으로써 데이터의 소거를 행하는 것을 특징으로 하는 불휘발성 반도체 메모리.
- 제1항 내지 제7항의 어느 한항에 있어서, 반도체층상에 형성된 필라(Pillar ;21)를 구비하고, 그 필라의 양측에 게이트 전극(5, 7, 9)이 형성된 것을 특징으로 하는 불휘발성 반도체 메모리.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP96-144428 | 1996-06-06 | ||
JP14442896A JP3123924B2 (ja) | 1996-06-06 | 1996-06-06 | 不揮発性半導体メモリ |
Publications (1)
Publication Number | Publication Date |
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KR980006435A true KR980006435A (ko) | 1998-03-30 |
Family
ID=15361973
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019970023328A KR980006435A (ko) | 1996-06-06 | 1997-06-05 | 불휘발성 반도체 메모리 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5898197A (ko) |
JP (1) | JP3123924B2 (ko) |
KR (1) | KR980006435A (ko) |
Families Citing this family (25)
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US6746893B1 (en) | 1997-07-29 | 2004-06-08 | Micron Technology, Inc. | Transistor with variable electron affinity gate and methods of fabrication and use |
US7154153B1 (en) | 1997-07-29 | 2006-12-26 | Micron Technology, Inc. | Memory device |
US6794255B1 (en) | 1997-07-29 | 2004-09-21 | Micron Technology, Inc. | Carburized silicon gate insulators for integrated circuits |
US7196929B1 (en) * | 1997-07-29 | 2007-03-27 | Micron Technology Inc | Method for operating a memory device having an amorphous silicon carbide gate insulator |
US6965123B1 (en) | 1997-07-29 | 2005-11-15 | Micron Technology, Inc. | Transistor with variable electron affinity gate and methods of fabrication and use |
US6936849B1 (en) | 1997-07-29 | 2005-08-30 | Micron Technology, Inc. | Silicon carbide gate transistor |
US6031263A (en) | 1997-07-29 | 2000-02-29 | Micron Technology, Inc. | DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate |
US6194267B1 (en) * | 1997-09-30 | 2001-02-27 | Texas Instruments Incorporated | Integrated circuit having independently formed array and peripheral isolation dielectrics |
US6034394A (en) | 1997-12-18 | 2000-03-07 | Advanced Micro Devices, Inc. | Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices |
US6046086A (en) * | 1998-06-19 | 2000-04-04 | Taiwan Semiconductor Manufacturing Company | Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash |
US6147904A (en) * | 1999-02-04 | 2000-11-14 | Tower Semiconductor Ltd. | Redundancy method and structure for 2-bit non-volatile memory cells |
KR100387267B1 (ko) * | 1999-12-22 | 2003-06-11 | 주식회사 하이닉스반도체 | 멀티 레벨 플래쉬 이이피롬 셀 및 그 제조 방법 |
JP4065671B2 (ja) * | 2001-08-31 | 2008-03-26 | シャープ株式会社 | 不揮発性半導体記憶装置、その製造方法及びその動作方法 |
DE10295303B4 (de) * | 2001-09-25 | 2017-07-13 | Sony Corporation | Nichtflüchtige Halbleiterspeichervorrichtung mit Ladungsspeicherfilm und Speicherperipherieschaltungen, Verfahren zu deren Betrieb und Verfahren zu deren Herstellung |
US7031196B2 (en) * | 2002-03-29 | 2006-04-18 | Macronix International Co., Ltd. | Nonvolatile semiconductor memory and operating method of the memory |
US7064978B2 (en) * | 2002-07-05 | 2006-06-20 | Aplus Flash Technology, Inc. | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout |
US6862223B1 (en) * | 2002-07-05 | 2005-03-01 | Aplus Flash Technology, Inc. | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout |
US6660588B1 (en) * | 2002-09-16 | 2003-12-09 | Advanced Micro Devices, Inc. | High density floating gate flash memory and fabrication processes therefor |
US6912163B2 (en) * | 2003-01-14 | 2005-06-28 | Fasl, Llc | Memory device having high work function gate and method of erasing same |
US6885590B1 (en) * | 2003-01-14 | 2005-04-26 | Advanced Micro Devices, Inc. | Memory device having A P+ gate and thin bottom oxide and method of erasing same |
EP1553635A1 (en) * | 2004-01-08 | 2005-07-13 | Macronix International Co., Ltd. | Nonvolatile semiconductor memory and operating method of the memory |
US7928005B2 (en) * | 2005-09-27 | 2011-04-19 | Advanced Micro Devices, Inc. | Method for forming narrow structures in a semiconductor device |
US7622349B2 (en) * | 2005-12-14 | 2009-11-24 | Freescale Semiconductor, Inc. | Floating gate non-volatile memory and method thereof |
FR2931289A1 (fr) * | 2008-05-13 | 2009-11-20 | St Microelectronics Rousset | Memoire a structure du type eeprom et a lecture seule |
JP5723340B2 (ja) | 2012-09-11 | 2015-05-27 | 株式会社東芝 | 不揮発性記憶装置の製造方法 |
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JPS5213782A (en) * | 1975-07-23 | 1977-02-02 | Hitachi Ltd | Semiconductor non-vol atile memory unit |
US4577215A (en) * | 1983-02-18 | 1986-03-18 | Rca Corporation | Dual word line, electrically alterable, nonvolatile floating gate memory device |
US5194924A (en) * | 1984-05-23 | 1993-03-16 | Hitachi, Ltd. | Semiconductor device of an LDD structure having a floating gate |
JPS61216482A (ja) * | 1985-03-22 | 1986-09-26 | Nec Corp | 不揮発性半導体記憶装置 |
US5111430A (en) * | 1989-06-22 | 1992-05-05 | Nippon Telegraph And Telephone Corporation | Non-volatile memory with hot carriers transmitted to floating gate through control gate |
JPH07105453B2 (ja) * | 1989-07-13 | 1995-11-13 | 株式会社東芝 | 半導体記憶装置のセル構造 |
DE69232311D1 (de) * | 1992-09-30 | 2002-01-31 | St Microelectronics Srl | Herstellungsverfahren von integrierten Vorrichtungen und so hergestellte integrierte Vorrichtung |
US5429969A (en) * | 1994-05-31 | 1995-07-04 | Motorola, Inc. | Process for forming electrically programmable read-only memory cell with a merged select/control gate |
JP2658910B2 (ja) * | 1994-10-28 | 1997-09-30 | 日本電気株式会社 | フラッシュメモリ装置およびその製造方法 |
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1996
- 1996-06-06 JP JP14442896A patent/JP3123924B2/ja not_active Expired - Fee Related
-
1997
- 1997-06-03 US US08/870,122 patent/US5898197A/en not_active Expired - Lifetime
- 1997-06-05 KR KR1019970023328A patent/KR980006435A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
JP3123924B2 (ja) | 2001-01-15 |
US5898197A (en) | 1999-04-27 |
JPH09326445A (ja) | 1997-12-16 |
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