KR980005871A - 반도체 장치 제조 방법 - Google Patents

반도체 장치 제조 방법 Download PDF

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Publication number
KR980005871A
KR980005871A KR1019960023643A KR19960023643A KR980005871A KR 980005871 A KR980005871 A KR 980005871A KR 1019960023643 A KR1019960023643 A KR 1019960023643A KR 19960023643 A KR19960023643 A KR 19960023643A KR 980005871 A KR980005871 A KR 980005871A
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South Korea
Prior art keywords
film
buffer
impurity
gate
high concentration
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KR1019960023643A
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KR100427032B1 (ko
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황준
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김주용
현대전자산업 주식회사
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Publication of KR100427032B1 publication Critical patent/KR100427032B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 모스트랜지스터의 소오스/드레인 형성과 게이트용 박막의 도핑을 한 번의 고농도 불순물 이온주입으로 실현하는 반도체 장치 제조방법에 있어서, 상기 게이트용 박막은 노출되고, 상기 소오스/드레인이 형성될 지역의 반도체 기판상에는 이온주입시의 완충역할을 하는 완충막을 형성된 상태에서 상기 고농도 불순물 이온주입을 실시하는 것을 특징으로 하는 반도체 장치 제조 방법에 관한 것으로, 게이트 전극에는 충분한 도핑이 이루어지고, 소오스/드레인은 얕게 형성할 수 있는 효과가 있다.

Description

반도체 장치 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a도 내지 제2f도는 본 발명의 일실시예에 따른 CMOS 제조 공정도.

Claims (10)

  1. 모스트랜지스터의 소오스/드레인 형성과 게이트용 박막의 도핑을 한 번의 고농도 불순물 이온주입으로 실현하는 반도체 장치 제조 방법에 있어서, 상기 게이트용 박막은 노출되고, 상기 소오스/드레인이 형성될 지역의 반도체 기판상에는 이온주입시의 완충역할을 하는 완충막을 형성된 상태에서 상기 고농도 불순물 이온주입을 실시하는 것을 특징으로 하는 반도체 장치 제조 방법.
  2. 제1항에 있어서, 상기 게이트용 박막은 비도핑된 폴리실리콘막인 것을 특징으로 하는 반도체 장치 제조 방법.
  3. 제1항에 있어서, 상기 완충막은 산화막인 것을 특징으로 하는 반도체 장치 제조 방법.
  4. 반도체 기판 상에 게이트 절연막, 게이트전극용 비도핑 폴리실리콘막, 및 상기 비도핑 폴리실리콘막을 보호하는 보호막을 차례로 형성하는 단계; 게이트 마스크를 사용하여 상기 보호막, 상기 비도핑 폴리실리콘막, 상기 게이트 절연막을 차례로 선택 식각하여 NMOS와 PMOS의 게이트 전극 패턴을 형성하는 단계; 저농도 불순물 이온주입을 실시하는 단계; 상기 선택식각되어 패턴화된 막들 측벽에 스페이서 절연막을 형성하는 단계; 노출된 상기 반도체 기판 상에 이온주입의 완충역할을 하는 완충막을 형성하는 단계; 상기 보호막을 제거하여 상기 비도핑 폴리실리콘막을 노출시키는 단계; 상기 NMOS와 PMOS의 어느 한측에 선택적으로 고농도 제1 불순물을 이온주입하는 단계; 및 상기 고농도 제1 불순물이 이온주입되지 않은 NMOS와 PMOS의 어느 한측에 선택적으로 고농도 제2불순물을 이온주입하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
  5. 제4항에 있어서, 상기 완충막은 산화공정에 의해 성장된 산화막인 것을 특징으로 하는 반도체 장치 제조 방법.
  6. 제5항에 있어서, 상기 보호막은 산화공정시 상기 비도핑 폴리실리콘막이 산화되는 것을 방지하는 것을 특징으로 하는 반도체 장치 제조 방법.
  7. 제6항에 있어서, 상기 보호막은 질화막인 것을 특징으로 하는 반도체 장치 제조 방법.
  8. 제7항에 있어서, 상기 질화막은 200~500㎛의 두께를 갖는 것을 특징으로 하는 반도체 장치 제조 방법.
  9. 제5항에 있어서, 상기 산화막은 200~700Å의 두께를 갖는 것을 특징으로 하는 반도체 장치 제조 방법.
  10. 제4항에 있어서, 상기 제1불순물 및 제2불순물은 서로 반대형은 n형 또는 p형 불순물인 것을 특징으로 하는 반도체 장치 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960023643A 1996-06-25 1996-06-25 반도체장치제조방법 KR100427032B1 (ko)

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KR1019960023643A KR100427032B1 (ko) 1996-06-25 1996-06-25 반도체장치제조방법

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100676194B1 (ko) * 2000-03-30 2007-01-30 삼성전자주식회사 씨모스(ｃｍｏｓ) 트랜지스터 제조방법

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100960923B1 (ko) 2006-12-28 2010-06-04 주식회사 하이닉스반도체 반도체 소자의 듀얼 폴리 게이트 형성방법
KR102111694B1 (ko) 2018-01-19 2020-05-18 주식회사 디월드 라벨부착장치

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930009048A (ko) * 1991-10-30 1993-05-22 김광호 폴리사이드 형성에 의한 반도체 장치의 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100676194B1 (ko) * 2000-03-30 2007-01-30 삼성전자주식회사 씨모스(ｃｍｏｓ) 트랜지스터 제조방법

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