KR980005520A - METHOD FOR FORMING METAL WIRING - Google Patents

METHOD FOR FORMING METAL WIRING Download PDF

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Publication number
KR980005520A
KR980005520A KR1019960024263A KR19960024263A KR980005520A KR 980005520 A KR980005520 A KR 980005520A KR 1019960024263 A KR1019960024263 A KR 1019960024263A KR 19960024263 A KR19960024263 A KR 19960024263A KR 980005520 A KR980005520 A KR 980005520A
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KR
South Korea
Prior art keywords
photoresist pattern
forming
photoresist
metal layer
pattern
Prior art date
Application number
KR1019960024263A
Other languages
Korean (ko)
Other versions
KR100220946B1 (en
Inventor
류달래
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960024263A priority Critical patent/KR100220946B1/en
Publication of KR980005520A publication Critical patent/KR980005520A/en
Application granted granted Critical
Publication of KR100220946B1 publication Critical patent/KR100220946B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 윗쪽이 좁고 아래쪽이 넓은 금속 배선을 형성함으로써 금속배선간의 간격(PITCH)이 좁은 경우에도 후속 공정에서 절연막을 형성할 때 한번의 화학 기상 증착으로 보이드를 방지하고, 막질이 우수한 절연막을 금속층간에 형성시킬 수 있으므로 결국 소자의 집적도를 높일 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a metal wiring of a semiconductor device, and more particularly, to a method of forming a metal wiring of a semiconductor device, It is possible to prevent voids and to form an insulating film having excellent film quality between the metal layers, and as a result, the degree of integration of the device can be increased.

Description

반도체 소자 금속배선 형성방법METHOD FOR FORMING METAL WIRING

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제5도 내지 제8도는 본 발명의 실시예에 의해 금속 배선을 형성하고, 그 상부에 절연막을 형성한 단면도.FIGS. 5 to 8 are cross-sectional views of a metal wiring formed according to an embodiment of the present invention and an insulating film formed on the metal wiring. FIG.

Claims (5)

반도체소자의 금속배선 제조방법에 있어서, 하부 박막 상부에 금속층을 증착하고, 그 상부에 감광막을 도포한 다음, 마스크를 이용한 노광 및 현성공정으로 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 가열하여 사부 모서리부분이 완만한 경사로 변한 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴과 하층의 노출된 금속층을 건식 식각의 방법으로 식각하여 상부 모서리가 식각되어 윗쪽이 좁고 아래쪽이 넓은 쐐기형태의 금속 배선을 형성하는 단계와, 상기 감광막 패턴의 남아 있는 부분을 제거하고, 전체 구조 상부에 층간 절연막을 형성하는 단계를 포함하는 반도체소자의 금속배선 형성방법.A method for fabricating a metal wiring of a semiconductor device, comprising the steps of: depositing a metal layer on an upper portion of a lower thin film, applying a photoresist on the metal thin film, forming a photoresist pattern by an exposure and a positive process using a mask, Forming a photoresist pattern having a gentle slope at a corner portion of the photoresist film pattern; etching the exposed metal layer by a dry etching method to etch the photoresist pattern and a lower metal layer to form a wedge-shaped metal wiring having a narrow upper portion and a wider upper portion; And removing the remaining portions of the photoresist pattern, and forming an interlayer insulating film on the entire structure. 제1항에 있어서, 상기 감광막 패턴과 하층의 노출된 금속층을 건식 식각할 때 감광막과 금속층간의 유사한 식각비로 설정하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method according to claim 1, wherein the dry etching of the photoresist pattern and the underlying metal layer is performed at a similar etch rate between the photoresist layer and the metal layer. 제1항에 있어서, 상기 감광막 패턴을 형성하는 공정에서 후공정에서 플로우(FLOW)과정의 효율을 톺이기 위해서 노광후 PEB 온도를 90-015℃정도에서 실행하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of manufacturing a semiconductor device according to claim 1, wherein the post-exposure PEB temperature is about 90-015 DEG C in order to reduce the efficiency of a flow in a subsequent step in the step of forming the photoresist pattern. / RTI > 제1항에 있어서, 상기 감공막 패턴을 형성하는 공정에서 후공정에서 플로우(FLOW)과정의 효율을 높이기 위해서 노광후 PEB공정을 생략하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method according to claim 1, wherein the post-exposure PEB process is omitted in order to increase the efficiency of the flow process in the post-process in the step of forming the protective film pattern. 제1항에 있어서, 상기 감광막 패턴을 플로우 시키는 온도는 180-250℃인 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method according to claim 1, wherein the temperature at which the photoresist pattern is flowed is 180-250 占 폚. ※참고사앙 : 최초출원 내용에 의하여 공개하는 것임.※ Reference: It is disclosed by the first application contents.
KR1019960024263A 1996-06-27 1996-06-27 Forming method for metal wiring of semiconductor device KR100220946B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960024263A KR100220946B1 (en) 1996-06-27 1996-06-27 Forming method for metal wiring of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960024263A KR100220946B1 (en) 1996-06-27 1996-06-27 Forming method for metal wiring of semiconductor device

Publications (2)

Publication Number Publication Date
KR980005520A true KR980005520A (en) 1998-03-30
KR100220946B1 KR100220946B1 (en) 1999-09-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960024263A KR100220946B1 (en) 1996-06-27 1996-06-27 Forming method for metal wiring of semiconductor device

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Publication number Publication date
KR100220946B1 (en) 1999-09-15

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