KR970705087A - 분산 버스 액세스 및 제어 조정에 따라 다수개의 내부 시그날 버스를 공유하는 다기능 집적회로(Integrated Circuit with Multiple Functions Sharing Multiple Internal Signal Buses According to Distributed Bus Access and Control Arbitration) - Google Patents

분산 버스 액세스 및 제어 조정에 따라 다수개의 내부 시그날 버스를 공유하는 다기능 집적회로(Integrated Circuit with Multiple Functions Sharing Multiple Internal Signal Buses According to Distributed Bus Access and Control Arbitration)

Info

Publication number
KR970705087A
KR970705087A KR1019970700551A KR19970700551A KR970705087A KR 970705087 A KR970705087 A KR 970705087A KR 1019970700551 A KR1019970700551 A KR 1019970700551A KR 19970700551 A KR19970700551 A KR 19970700551A KR 970705087 A KR970705087 A KR 970705087A
Authority
KR
South Korea
Prior art keywords
integrated circuit
internal signal
bus access
signal buses
distributed bus
Prior art date
Application number
KR1019970700551A
Other languages
English (en)
Other versions
KR100403405B1 (ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR970705087A publication Critical patent/KR970705087A/ko
Application granted granted Critical
Publication of KR100403405B1 publication Critical patent/KR100403405B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G06F11/3652—Software debugging using additional hardware in-circuit-emulation [ICE] arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Microcomputers (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
KR1019970700551A 1995-05-26 1996-05-16 분산형버스액세스및제어조정에따라다수개의내부신호버스를공유하는다수개의회로기능요소를갖는집적회로 KR100403405B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45150395A 1995-05-26 1995-05-26
US08/451,503 1995-05-26

Publications (2)

Publication Number Publication Date
KR970705087A true KR970705087A (ko) 1997-09-06
KR100403405B1 KR100403405B1 (ko) 2004-03-30

Family

ID=23792487

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970700551A KR100403405B1 (ko) 1995-05-26 1996-05-16 분산형버스액세스및제어조정에따라다수개의내부신호버스를공유하는다수개의회로기능요소를갖는집적회로

Country Status (5)

Country Link
US (2) US5774684A (ko)
EP (2) EP1343076A3 (ko)
KR (1) KR100403405B1 (ko)
DE (1) DE69633166T2 (ko)
WO (1) WO1996037854A2 (ko)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2976850B2 (ja) * 1995-07-13 1999-11-10 日本電気株式会社 データ処理装置
US5968155A (en) * 1995-08-23 1999-10-19 Sun Microsystems, Inc. Digital gate computer bus
JP3743789B2 (ja) * 1996-10-24 2006-02-08 株式会社ルネサステクノロジ メモリとプロセサとが同一チップ上に形成されたマイクロコンピュータ
JPH10214201A (ja) * 1997-01-29 1998-08-11 Mitsubishi Electric Corp マイクロコンピュータ
US5978866A (en) * 1997-03-10 1999-11-02 Integrated Technology Express, Inc. Distributed pre-fetch buffer for multiple DMA channel device
US5978902A (en) * 1997-04-08 1999-11-02 Advanced Micro Devices, Inc. Debug interface including operating system access of a serial/parallel debug port
US6189140B1 (en) 1997-04-08 2001-02-13 Advanced Micro Devices, Inc. Debug interface including logic generating handshake signals between a processor, an input/output port, and a trace logic
US6154856A (en) * 1997-04-08 2000-11-28 Advanced Micro Devices, Inc. Debug interface including state machines for timing synchronization and communication
US6148381A (en) * 1997-04-08 2000-11-14 Advanced Micro Devices, Inc. Single-port trace buffer architecture with overflow reduction
US6108738A (en) * 1997-06-10 2000-08-22 Vlsi Technology, Inc. Multi-master PCI bus system within a single integrated circuit
US6128728A (en) 1997-08-01 2000-10-03 Micron Technology, Inc. Virtual shadow registers and virtual register windows
GB2329049B (en) * 1997-09-09 2002-09-11 Advanced Risc Mach Ltd Apparatus and method for identifying exceptions when debugging software
TW406229B (en) * 1997-11-06 2000-09-21 Hitachi Ltd Data process system and microcomputer
US6105125A (en) * 1997-11-12 2000-08-15 National Semiconductor Corporation High speed, scalable microcode based instruction decoder for processors using split microROM access, dynamic generic microinstructions, and microcode with predecoded instruction information
US6009261A (en) * 1997-12-16 1999-12-28 International Business Machines Corporation Preprocessing of stored target routines for emulating incompatible instructions on a target processor
US6041380A (en) * 1998-01-21 2000-03-21 Micron Electronics, Inc. Method for increasing the number of devices capable of being operably connected to a host bus
US6263389B1 (en) 1998-01-21 2001-07-17 Micron Technology, Inc. Apparatus for increasing the number of loads supported by a host bus
US6073200A (en) * 1998-01-27 2000-06-06 Vlsi Technology, Inc. System having processor monitoring capability of an integrated circuits buried, internal bus for use with a plurality of internal masters and a method therefor
US6289300B1 (en) 1998-02-06 2001-09-11 Analog Devices, Inc. Integrated circuit with embedded emulator and emulation system for use with such an integrated circuit
US6385689B1 (en) 1998-02-06 2002-05-07 Analog Devices, Inc. Memory and a data processor including a memory
EP0935195A2 (en) 1998-02-06 1999-08-11 Analog Devices, Inc. "An integrated circuit with a high resolution analog-to-digital converter, a microcontroller and high density memory and an emulator for an integrated circuit
US6701395B1 (en) 1998-02-06 2004-03-02 Analog Devices, Inc. Analog-to-digital converter that preseeds memory with channel identifier data and makes conversions at fixed rate with direct memory access
US6145100A (en) * 1998-03-04 2000-11-07 Advanced Micro Devices, Inc. Debug interface including timing synchronization logic
US6145123A (en) * 1998-07-01 2000-11-07 Advanced Micro Devices, Inc. Trace on/off with breakpoint register
US6567518B1 (en) * 1998-08-28 2003-05-20 Teltronics, Inc. Method of field programmable gate array configuration
US6467009B1 (en) * 1998-10-14 2002-10-15 Triscend Corporation Configurable processor system unit
US6330645B1 (en) 1998-12-21 2001-12-11 Cisco Technology, Inc. Multi-stream coherent memory controller apparatus and method
US6618777B1 (en) * 1999-01-21 2003-09-09 Analog Devices, Inc. Method and apparatus for communicating between multiple functional units in a computer environment
US6609169B1 (en) 1999-06-14 2003-08-19 Jay Powell Solid-state audio-video playback system
US6449672B1 (en) * 1999-07-21 2002-09-10 Apple Computer, Inc. PCI device arbiter
US6671836B1 (en) * 1999-09-23 2003-12-30 Rambus Inc. Method and apparatus for testing memory
US6851047B1 (en) 1999-10-15 2005-02-01 Xilinx, Inc. Configuration in a configurable system on a chip
GB2362729B (en) 1999-12-23 2004-02-11 St Microelectronics Sa Memory access debug facility
GB2365546B (en) * 1999-12-23 2004-02-18 St Microelectronics Sa A computer system with two debug watch modes
GB2366006B (en) 1999-12-23 2004-06-30 St Microelectronics Sa A computer system with debug facility
GB2362968B (en) 1999-12-23 2003-12-10 St Microelectronics Sa Computer system with debug facility
GB2362730B (en) 1999-12-23 2004-02-11 St Microelectronics Sa Computer register watch
US6519670B1 (en) * 2000-02-04 2003-02-11 Koninklijke Philips Electronics N.V. Method and system for optimizing a host bus that directly interfaces to a 16-bit PCMCIA host bus adapter
US6721840B1 (en) 2000-08-18 2004-04-13 Triscend Corporation Method and system for interfacing an integrated circuit to synchronous dynamic memory and static memory
US6754760B1 (en) 2000-08-21 2004-06-22 Xilinx, Inc. Programmable interface for a configurable system bus
US6518787B1 (en) 2000-09-21 2003-02-11 Triscend Corporation Input/output architecture for efficient configuration of programmable input/output cells
US7139848B1 (en) 2000-12-08 2006-11-21 Xilinx, Inc. DMA protocol extension for packet-based transfer
US7036033B1 (en) * 2001-01-04 2006-04-25 3Pardata, Inc. Disk enclosure with multiplexers for connecting 12C buses in multiple power domains
US6725364B1 (en) 2001-03-08 2004-04-20 Xilinx, Inc. Configurable processor system
TWI223138B (en) * 2001-07-11 2004-11-01 Faraday Tech Corp Device and method for detecting micro-processor execution performance
US7107374B1 (en) 2001-09-05 2006-09-12 Xilinx, Inc. Method for bus mastering for devices resident in configurable system logic
WO2003029997A1 (en) * 2001-09-27 2003-04-10 Koninklijke Philips Electronics N.V. Bus system and bus interface
US7305469B2 (en) * 2001-12-18 2007-12-04 Ebay Inc. Prioritization of third party access to an online commerce site
US7570651B2 (en) * 2004-06-16 2009-08-04 Siamack Haghighi High-performance reconfigurable interconnect for concurrent operation of multiple systems
US7461190B2 (en) * 2005-08-11 2008-12-02 P.A. Semi, Inc. Non-blocking address switch with shallow per agent queues
US8875798B2 (en) * 2009-04-27 2014-11-04 National Oilwell Varco, L.P. Wellsite replacement system and method for using same
DE102010003521A1 (de) * 2010-03-31 2011-10-06 Robert Bosch Gmbh Modulare Struktur zur Datenverarbeitung
EP2372490A1 (en) * 2010-03-31 2011-10-05 Robert Bosch GmbH Circuit arrangement for a data processing system and method for data processing
US8806093B2 (en) * 2010-04-01 2014-08-12 Intel Corporation Method, apparatus, and system for enabling a deterministic interface
US9176913B2 (en) 2011-09-07 2015-11-03 Apple Inc. Coherence switch for I/O traffic
US10198849B1 (en) * 2017-10-26 2019-02-05 Advanced Micro Devices, Inc. Preloading translation and data caches using on-chip DMA engine with fast data discard
EP3884558A4 (en) 2019-01-31 2022-08-17 General Electric Company BATTERY CHARGE AND DISCHARGE POWER CONTROL IN AN ELECTRICAL NETWORK
US11782838B2 (en) 2020-08-14 2023-10-10 Advanced Micro Devices, Inc. Command processor prefetch techniques

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4674089A (en) * 1985-04-16 1987-06-16 Intel Corporation In-circuit emulator
US4926323A (en) * 1988-03-03 1990-05-15 Advanced Micro Devices, Inc. Streamlined instruction processor
JPH02103482A (ja) * 1988-10-13 1990-04-16 Matsushita Graphic Commun Syst Inc 集積回路装置
US5226126A (en) * 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
US5204953A (en) * 1989-08-04 1993-04-20 Intel Corporation One clock address pipelining in segmentation unit
US5222240A (en) * 1990-02-14 1993-06-22 Intel Corporation Method and apparatus for delaying writing back the results of instructions to a processor
US5259006A (en) * 1990-04-18 1993-11-02 Quickturn Systems, Incorporated Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like
EP0453268B1 (en) * 1990-04-20 1997-10-22 Hitachi, Ltd. A microprocessor for inserting a bus cycle to output an internal information for an emulation
CA2045798A1 (en) * 1990-06-29 1991-12-30 Rebecca L. Stamm Conversion of internal processor register commands to i/o space addresses
US5226047A (en) * 1990-10-03 1993-07-06 Chips And Technologies, Inc. In-circuit emulation of a microprocessor mounted on a circuit board
US5321828A (en) * 1991-06-07 1994-06-14 Step Engineering High speed microcomputer in-circuit emulator
US5241631A (en) * 1991-08-23 1993-08-31 Nec Technologies, Inc. Personal computer having a local bus interface to a video circuit
US5189319A (en) * 1991-10-10 1993-02-23 Intel Corporation Power reducing buffer/latch circuit
EP0545581B1 (en) * 1991-12-06 1999-04-21 National Semiconductor Corporation Integrated data processing system including CPU core and parallel, independently operating DSP module
US5254888A (en) * 1992-03-27 1993-10-19 Picopower Technology Inc. Switchable clock circuit for microprocessors to thereby save power
US5542058A (en) * 1992-07-06 1996-07-30 Digital Equipment Corporation Pipelined computer with operand context queue to simplify context-dependent execution flow
US5396634A (en) * 1992-09-30 1995-03-07 Intel Corporation Method and apparatus for increasing the decoding speed of a microprocessor
JP3524110B2 (ja) * 1992-11-06 2004-05-10 株式会社ルネサステクノロジ マイクロコンピュータシステム
US5522050A (en) * 1993-05-28 1996-05-28 International Business Machines Corporation Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus
US5574892A (en) * 1993-06-30 1996-11-12 Intel Corporation Use of between-instruction breaks to implement complex in-circuit emulation features
US5440747A (en) * 1993-09-27 1995-08-08 Hitachi America, Ltd. Data processor with control logic for storing operation mode status and associated method
US5404473A (en) * 1994-03-01 1995-04-04 Intel Corporation Apparatus and method for handling string operations in a pipelined processor
US5619726A (en) * 1994-10-11 1997-04-08 Intel Corporation Apparatus and method for performing arbitration and data transfer over multiple buses
US5619728A (en) * 1994-10-20 1997-04-08 Dell Usa, L.P. Decoupled DMA transfer list storage technique for a peripheral resource controller
US5630102A (en) * 1994-12-19 1997-05-13 Intel Corporation In-circuit-emulation event management system

Also Published As

Publication number Publication date
EP0776504B1 (en) 2004-08-18
KR100403405B1 (ko) 2004-03-30
EP0776504A2 (en) 1997-06-04
DE69633166D1 (de) 2004-09-23
EP1343076A2 (en) 2003-09-10
EP1343076A3 (en) 2004-02-25
DE69633166T2 (de) 2005-08-18
WO1996037854A2 (en) 1996-11-28
US5774684A (en) 1998-06-30
WO1996037854A3 (en) 1997-08-07
US5857094A (en) 1999-01-05

Similar Documents

Publication Publication Date Title
KR970705087A (ko) 분산 버스 액세스 및 제어 조정에 따라 다수개의 내부 시그날 버스를 공유하는 다기능 집적회로(Integrated Circuit with Multiple Functions Sharing Multiple Internal Signal Buses According to Distributed Bus Access and Control Arbitration)
DE69230428T2 (de) Verklemmungserkennung und Maskierung enthaltende Busarbitrierungsarchitektur
DE69626231D1 (de) Bus-Master-Arbitrierungssschaltung mit einer Vielzahl von Arbitern
DE69423056T2 (de) Arbitrierungslogik für Mehrfachbus-Rechnersystem
DE69021603T2 (de) Buszugriffsarbitrierung in digitalen Rechnern.
DE68925763T2 (de) Verbindungs- und Zugriffsarbitrierungsanordnung für Multiprozessorsystem
DE69132344D1 (de) Dynamische Busarbitrierung
KR970700879A (ko) 멀티프로세서 시스템에서 버스의 병렬 액세스를 위한 신호화 프로토콜(improved signaling protocol for concurrent bus access in a multiprocessor system)
DE68927626D1 (de) Hierarchisches Mehrfachbus-Computersystem
DE69628609D1 (de) Distribuiertes Pipeline-Busarbitrierungssystem
DE69602091D1 (de) Erweiterungskarte mit ein-/ausschaltbarem festwertspeicher für pci-busrechner und entsprechende schnittstelle
FI955751A0 (fi) Paikallisten tietoliikenneväyläjärjestelmien yhteen liittäminen
DE69433130D1 (de) Rechnersystem mit verändertem lokalen Datenbus
DE69632289D1 (de) Verteiltes serielles Arbitrierungssystem
DE69615327D1 (de) Logische Adressbusarchitektur für Mehrprozessorsysteme
DE69228919T2 (de) Tristate-Treiberschaltung für interne Datenbusleitungen
DE69612092D1 (de) Digitales datenbussystem mit arbitrierung
DE59510974D1 (de) Bus-Treiberschaltung
FR2650414B1 (fr) Architecture de systeme informatique comportant deux bus
KR970045644U (ko) 버스 중재회로
KR970038406U (ko) 버스의 엔진과 라디에이터 분리격벽
KR940017068U (ko) 후면버스 사용 시스템에서의 세그먼트 중재버스 회로
KR950010352U (ko) 지역 버스 중재 회로
WO1996010904A3 (en) Digital signal processor
KR970047757U (ko) 정적램 사용권 중재회로

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20091013

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee