KR970700879A - 멀티프로세서 시스템에서 버스의 병렬 액세스를 위한 신호화 프로토콜(improved signaling protocol for concurrent bus access in a multiprocessor system) - Google Patents

멀티프로세서 시스템에서 버스의 병렬 액세스를 위한 신호화 프로토콜(improved signaling protocol for concurrent bus access in a multiprocessor system)

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Publication number
KR970700879A
KR970700879A KR1019960703806A KR19960703806A KR970700879A KR 970700879 A KR970700879 A KR 970700879A KR 1019960703806 A KR1019960703806 A KR 1019960703806A KR 19960703806 A KR19960703806 A KR 19960703806A KR 970700879 A KR970700879 A KR 970700879A
Authority
KR
South Korea
Prior art keywords
multiprocessor system
signaling protocol
access
buses
improved
Prior art date
Application number
KR1019960703806A
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English (en)
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KR100305138B1 (ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR970700879A publication Critical patent/KR970700879A/ko
Application granted granted Critical
Publication of KR100305138B1 publication Critical patent/KR100305138B1/ko

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
KR1019960703806A 1994-01-14 1995-01-06 멀티프로세서 시스템에서 버스의 병렬 액세스를 위한 신호화 프 로토콜 KR100305138B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/181,900 US5426740A (en) 1994-01-14 1994-01-14 Signaling protocol for concurrent bus access in a multiprocessor system
US08/181,900 1994-01-14
PCT/US1995/000173 WO1995019600A1 (en) 1994-01-14 1995-01-06 Improved signaling protocol for concurrent bus access in a multiprocessor system

Publications (2)

Publication Number Publication Date
KR970700879A true KR970700879A (ko) 1997-02-12
KR100305138B1 KR100305138B1 (ko) 2001-11-22

Family

ID=22666285

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960703806A KR100305138B1 (ko) 1994-01-14 1995-01-06 멀티프로세서 시스템에서 버스의 병렬 액세스를 위한 신호화 프 로토콜

Country Status (5)

Country Link
US (1) US5426740A (ko)
KR (1) KR100305138B1 (ko)
CN (1) CN1111799C (ko)
AU (1) AU1523595A (ko)
WO (1) WO1995019600A1 (ko)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761450A (en) * 1994-02-24 1998-06-02 Intel Corporation Bus bridge circuit flushing buffer to a bus during one acquire/relinquish cycle by providing empty address indications
WO1996008773A2 (en) * 1994-09-16 1996-03-21 Cirrus Logic, Inc. Pcmcia dma data bus mastering
US5568619A (en) * 1995-01-05 1996-10-22 International Business Machines Corporation Method and apparatus for configuring a bus-to-bus bridge
JPH096718A (ja) * 1995-06-16 1997-01-10 Toshiba Corp ポータブルコンピュータシステム
US5761444A (en) * 1995-09-05 1998-06-02 Intel Corporation Method and apparatus for dynamically deferring transactions
US5926378A (en) * 1995-09-29 1999-07-20 International Business Machines Corporation Low profile riser card assembly using paired back-to-back peripheral card connectors mounted on universal footprints supporting different bus form factors
US5587957A (en) * 1995-09-29 1996-12-24 Intel Corporation Circuit for sharing a memory of a microcontroller with an external device
US5796964A (en) * 1996-01-16 1998-08-18 International Business Machines Method for modifying an existing computer bus to enhance system performance
US5850557A (en) * 1996-05-10 1998-12-15 Intel Corporation Method and apparatus for reducing bus bridge thrashing by temporarily masking agent requests to allow conflicting requests to be completed
KR980004067A (ko) * 1996-06-25 1998-03-30 김광호 멀티프로세서 시스템의 데이터 송수신장치 및 방법
US5845107A (en) * 1996-07-03 1998-12-01 Intel Corporation Signaling protocol conversion between a processor and a high-performance system bus
US5771358A (en) * 1996-07-15 1998-06-23 Micron Electronics, Inc. Method and system for apportioning computer bus bandwidth
US6115551A (en) * 1997-03-27 2000-09-05 Industrial Technology Research Institute System for minimizing the number of control signals and maximizing channel utilization between an I/O bridge and a data buffer
US5905913A (en) * 1997-04-24 1999-05-18 International Business Machines Corporation System for collecting a specified number of peripheral interrupts and transferring the interrupts as a group to the processor
US6173346B1 (en) 1997-05-13 2001-01-09 Micron Electronics, Inc. Method for hot swapping a programmable storage adapter using a programmable processor for selectively enabling or disabling power to adapter slot in response to respective request signals
US6243838B1 (en) 1997-05-13 2001-06-05 Micron Electronics, Inc. Method for automatically reporting a system failure in a server
US6179486B1 (en) 1997-05-13 2001-01-30 Micron Electronics, Inc. Method for hot add of a mass storage adapter on a system including a dynamically loaded adapter driver
US6253334B1 (en) 1997-05-13 2001-06-26 Micron Electronics, Inc. Three bus server architecture with a legacy PCI bus and mirrored I/O PCI buses
US6269412B1 (en) 1997-05-13 2001-07-31 Micron Technology, Inc. Apparatus for recording information system events
US6249828B1 (en) 1997-05-13 2001-06-19 Micron Electronics, Inc. Method for the hot swap of a mass storage adapter on a system including a statically loaded adapter driver
US6304929B1 (en) 1997-05-13 2001-10-16 Micron Electronics, Inc. Method for hot swapping a programmable adapter by using a programmable processor to selectively disabling and enabling power thereto upon receiving respective control signals
US6170028B1 (en) 1997-05-13 2001-01-02 Micron Electronics, Inc. Method for hot swapping a programmable network adapter by using a programmable processor to selectively disabling and enabling power thereto upon receiving respective control signals
US6202111B1 (en) 1997-05-13 2001-03-13 Micron Electronics, Inc. Method for the hot add of a network adapter on a system including a statically loaded adapter driver
US6192434B1 (en) 1997-05-13 2001-02-20 Micron Electronics, Inc System for hot swapping a programmable adapter by using a programmable processor to selectively disabling and enabling power thereto upon receiving respective control signals
US6163853A (en) 1997-05-13 2000-12-19 Micron Electronics, Inc. Method for communicating a software-generated pulse waveform between two servers in a network
US6499073B1 (en) 1997-05-13 2002-12-24 Micron Electronics, Inc. System using programmable processor for selectively enabling or disabling power to adapter in response to respective request signals
US6247080B1 (en) 1997-05-13 2001-06-12 Micron Electronics, Inc. Method for the hot add of devices
US6073190A (en) * 1997-07-18 2000-06-06 Micron Electronics, Inc. System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair
KR100256944B1 (ko) * 1997-07-31 2000-05-15 윤종용 피씨아이 핫 플러그를 위한 경보 장치
US6115770A (en) * 1998-03-25 2000-09-05 Lsi Logic Corporation System and method for coordinating competing register accesses by multiple buses
US6421746B1 (en) * 1998-03-26 2002-07-16 Micron Electronics, Inc. Method of data and interrupt posting for computer devices
US6587961B1 (en) * 1998-06-15 2003-07-01 Sun Microsystems, Inc. Multi-processor system bridge with controlled access
US6260098B1 (en) * 1998-12-17 2001-07-10 International Business Machines Corporation Shared peripheral controller
US6725312B1 (en) 2000-11-02 2004-04-20 Cml Versatel Inc. Bus architecture for high reliability communications in computer system
US6810455B2 (en) 2001-09-28 2004-10-26 Cradle Technologies, Inc. Bus arbitration system and method for carrying out a centralized arbitration with independent bus request and grant lines
TWI425354B (zh) * 2007-10-16 2014-02-01 Mstar Semiconductor Inc 資料存取系統及方法
CN102087637B (zh) * 2009-12-02 2012-08-22 奇景光电股份有限公司 利用率增强的共享汇流排系统及汇流排仲裁方法
CN101937537A (zh) * 2010-10-25 2011-01-05 上海申瑞电力科技股份有限公司 电网历史数据的并行访问方法
CN109818843A (zh) * 2019-02-26 2019-05-28 北京龙鼎源科技股份有限公司 总线的监听解析方法及设备、存储介质和电子装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3959775A (en) * 1974-08-05 1976-05-25 Gte Automatic Electric Laboratories Incorporated Multiprocessing system implemented with microprocessors
JPS58225432A (ja) * 1982-06-24 1983-12-27 Toshiba Corp 要求バツフア装置
JPS60258671A (ja) * 1984-06-05 1985-12-20 Nec Corp プロセツサ
US4837682A (en) * 1987-04-07 1989-06-06 Glen Culler & Associates Bus arbitration system and method
US5280589A (en) * 1987-07-30 1994-01-18 Kabushiki Kaisha Toshiba Memory access control system for use with a relatively small size data processing system
US5327545A (en) * 1988-05-26 1994-07-05 International Business Machines Corporation Data processing apparatus for selectively posting write cycles using the 82385 cache controller
US5261057A (en) * 1988-06-30 1993-11-09 Wang Laboratories, Inc. I/O bus to system interface
US5003463A (en) * 1988-06-30 1991-03-26 Wang Laboratories, Inc. Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
US5065313A (en) * 1989-03-30 1991-11-12 Dell Usa Corporation Digital computer system having circuit for regulation of I/O command recovery time
US5170481A (en) * 1989-06-19 1992-12-08 International Business Machines Corporation Microprocessor hold and lock circuitry
US5220651A (en) * 1989-10-11 1993-06-15 Micral, Inc. Cpu-bus controller for accomplishing transfer operations between a controller and devices coupled to an input/output bus
US5125080A (en) * 1989-11-13 1992-06-23 Chips And Technologies, Incorporated Logic support chip for AT-type computer with improved bus architecture
US5253348A (en) * 1990-12-28 1993-10-12 Apple Computer, Inc. Method of arbitration for buses operating at different speeds
US5353417A (en) * 1991-05-28 1994-10-04 International Business Machines Corp. Personal computer with bus interface controller coupled directly with local processor and input/output data buses and for anticipating memory control changes on arbitration for bus access
US5263139A (en) * 1992-05-19 1993-11-16 Sun Microsystems, Inc. Multiple bus architecture for flexible communication among processor modules and memory subsystems and specialized subsystems

Also Published As

Publication number Publication date
KR100305138B1 (ko) 2001-11-22
WO1995019600A1 (en) 1995-07-20
US5426740A (en) 1995-06-20
AU1523595A (en) 1995-08-01
CN1111799C (zh) 2003-06-18
CN1143421A (zh) 1997-02-19

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