DE69632634D1 - Arbitrierungseinheit zum Multiprozessorsystembuszugriff mit Wiederholungsfähigkeit - Google Patents

Arbitrierungseinheit zum Multiprozessorsystembuszugriff mit Wiederholungsfähigkeit

Info

Publication number
DE69632634D1
DE69632634D1 DE69632634T DE69632634T DE69632634D1 DE 69632634 D1 DE69632634 D1 DE 69632634D1 DE 69632634 T DE69632634 T DE 69632634T DE 69632634 T DE69632634 T DE 69632634T DE 69632634 D1 DE69632634 D1 DE 69632634D1
Authority
DE
Germany
Prior art keywords
repeatability
system bus
multiprocessor system
arbitration unit
bus access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69632634T
Other languages
English (en)
Other versions
DE69632634T2 (de
Inventor
Ferruccio Zulian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SAS
Original Assignee
Bull SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SAS filed Critical Bull SAS
Application granted granted Critical
Publication of DE69632634D1 publication Critical patent/DE69632634D1/de
Publication of DE69632634T2 publication Critical patent/DE69632634T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69632634T 1996-12-13 1996-12-13 Arbitrierungseinheit zum Multiprozessorsystembuszugriff mit Wiederholungsfähigkeit Expired - Lifetime DE69632634T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP96830621A EP0848332B1 (de) 1996-12-13 1996-12-13 Arbitrierungseinheit zum Multiprozessorsystembuszugriff mit Wiederholungsfähigkeit

Publications (2)

Publication Number Publication Date
DE69632634D1 true DE69632634D1 (de) 2004-07-08
DE69632634T2 DE69632634T2 (de) 2005-06-09

Family

ID=8226074

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69632634T Expired - Lifetime DE69632634T2 (de) 1996-12-13 1996-12-13 Arbitrierungseinheit zum Multiprozessorsystembuszugriff mit Wiederholungsfähigkeit

Country Status (3)

Country Link
US (1) US5941967A (de)
EP (1) EP0848332B1 (de)
DE (1) DE69632634T2 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
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US6330632B1 (en) * 1998-09-30 2001-12-11 Hewlett-Packard Company System for arbitrating access from multiple requestors to multiple shared resources over a shared communications link and giving preference for accessing idle shared resources
US6502150B1 (en) * 1998-12-03 2002-12-31 Intel Corporation Method and apparatus for resource sharing in a multi-processor system
US6718422B1 (en) * 1999-07-29 2004-04-06 International Business Machines Corporation Enhanced bus arbiter utilizing variable priority and fairness
US6704822B1 (en) * 1999-10-01 2004-03-09 Sun Microsystems, Inc. Arbitration protocol for a shared data cache
US7558923B1 (en) * 1999-12-22 2009-07-07 Intel Corporation Prevention of live-lock in a multi-processor system
US6523098B1 (en) * 1999-12-22 2003-02-18 Intel Corporation Mechanism for efficient low priority write draining
US6701397B1 (en) * 2000-03-21 2004-03-02 International Business Machines Corporation Pre-arbitration request limiter for an integrated multi-master bus system
US6816923B1 (en) * 2000-07-31 2004-11-09 Webtv Networks, Inc. Arbitrating and servicing polychronous data requests in direct memory access
US6826619B1 (en) 2000-08-21 2004-11-30 Intel Corporation Method and apparatus for preventing starvation in a multi-node architecture
US6487643B1 (en) 2000-09-29 2002-11-26 Intel Corporation Method and apparatus for preventing starvation in a multi-node architecture
US6516393B1 (en) 2000-09-29 2003-02-04 International Business Machines Corporation Dynamic serialization of memory access in a multi-processor system
US6658510B1 (en) 2000-10-18 2003-12-02 International Business Machines Corporation Software method to retry access to peripherals that can cause bus timeouts during momentary busy periods
US6772298B2 (en) 2000-12-20 2004-08-03 Intel Corporation Method and apparatus for invalidating a cache line without data return in a multi-node architecture
US7234029B2 (en) 2000-12-28 2007-06-19 Intel Corporation Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
US6791412B2 (en) * 2000-12-28 2004-09-14 Intel Corporation Differential amplifier output stage
US20020087775A1 (en) * 2000-12-29 2002-07-04 Looi Lily P. Apparatus and method for interrupt delivery
US6721918B2 (en) 2000-12-29 2004-04-13 Intel Corporation Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect
US6971098B2 (en) 2001-06-27 2005-11-29 Intel Corporation Method and apparatus for managing transaction requests in a multi-node architecture
US7111298B1 (en) * 2001-09-04 2006-09-19 Emc Corporation Inter-processor competition for a shared resource
US6973520B2 (en) * 2002-07-11 2005-12-06 International Business Machines Corporation System and method for providing improved bus utilization via target directed completion
US7065596B2 (en) * 2002-09-19 2006-06-20 Intel Corporation Method and apparatus to resolve instruction starvation
US7096289B2 (en) * 2003-01-16 2006-08-22 International Business Machines Corporation Sender to receiver request retry method and apparatus
US20060041705A1 (en) * 2004-08-20 2006-02-23 International Business Machines Corporation System and method for arbitration between shared peripheral core devices in system on chip architectures
JP2007087247A (ja) * 2005-09-26 2007-04-05 Nec Electronics Corp バス制御システム
WO2008018969A1 (en) * 2006-08-04 2008-02-14 Parallel Computers Technology, Inc. Apparatus and method of optimizing database clustering with zero transaction loss
US20080091879A1 (en) * 2006-10-12 2008-04-17 International Business Machines Corporation Method and structure for interruting L2 cache live-lock occurrences
US20080270658A1 (en) * 2007-04-27 2008-10-30 Matsushita Electric Industrial Co., Ltd. Processor system, bus controlling method, and semiconductor device
US7739455B2 (en) * 2007-06-22 2010-06-15 Mips Technologies, Inc. Avoiding livelock using a cache manager in multiple core processors
US7769958B2 (en) * 2007-06-22 2010-08-03 Mips Technologies, Inc. Avoiding livelock using intervention messages in multiple core processors
US7747803B2 (en) * 2007-11-28 2010-06-29 International Business Machines Corporation Device, system, and method of handling delayed transactions
KR101420290B1 (ko) * 2008-05-14 2014-07-17 삼성전자주식회사 트랜잭션들을 그룹화하는 버스 중재기, 이를 포함하는 버스장치 및 시스템
JP5127927B2 (ja) * 2008-08-22 2013-01-23 三菱電機株式会社 バスコントローラ及びバス通信システム及びバス制御方法
JP2010286983A (ja) * 2009-06-10 2010-12-24 Renesas Electronics Corp バス調停回路及びバス調停方法
US8984194B2 (en) * 2011-01-21 2015-03-17 Numia Medical Technology Llc Multi-master bus arbitration and resource control
US9298507B2 (en) 2013-09-26 2016-03-29 International Business Machines Corporation Data processing resource management
US11875183B2 (en) * 2018-05-30 2024-01-16 Texas Instruments Incorporated Real-time arbitration of shared resources in a multi-master communication and control system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05324544A (ja) * 1992-05-15 1993-12-07 Hitachi Ltd バス制御方法
CA2140685A1 (en) * 1994-01-28 1995-07-29 Randy M. Bonella Bus master arbitration circuitry having improved prioritization
WO1996035175A2 (en) * 1995-05-02 1996-11-07 Apple Computer, Inc. Deadlock avoidance in a split-bus computer system
US5706446A (en) * 1995-05-18 1998-01-06 Unisys Corporation Arbitration system for bus requestors with deadlock prevention
US5781745A (en) * 1996-05-20 1998-07-14 3Com Corporation High speed communication bus

Also Published As

Publication number Publication date
DE69632634T2 (de) 2005-06-09
EP0848332B1 (de) 2004-06-02
EP0848332A1 (de) 1998-06-17
US5941967A (en) 1999-08-24

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: BULL S.A., LES CLAYES SOUS BOIS, FR

8364 No opposition during term of opposition