DE69729782D1 - Busarbiter - Google Patents

Busarbiter

Info

Publication number
DE69729782D1
DE69729782D1 DE69729782T DE69729782T DE69729782D1 DE 69729782 D1 DE69729782 D1 DE 69729782D1 DE 69729782 T DE69729782 T DE 69729782T DE 69729782 T DE69729782 T DE 69729782T DE 69729782 D1 DE69729782 D1 DE 69729782D1
Authority
DE
Germany
Prior art keywords
bus arbiter
arbiter
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69729782T
Other languages
English (en)
Other versions
DE69729782T2 (de
Inventor
Midori Yasuda
Masashi Kamada
Takayuki Ninomiya
Kazuhiko Morimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of DE69729782D1 publication Critical patent/DE69729782D1/de
Application granted granted Critical
Publication of DE69729782T2 publication Critical patent/DE69729782T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
DE69729782T 1996-12-26 1997-12-24 Busarbiter Expired - Lifetime DE69729782T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP35650496 1996-12-26
JP8356504A JPH10187600A (ja) 1996-12-26 1996-12-26 バスアービタ

Publications (2)

Publication Number Publication Date
DE69729782D1 true DE69729782D1 (de) 2004-08-12
DE69729782T2 DE69729782T2 (de) 2005-07-07

Family

ID=18449355

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69729782T Expired - Lifetime DE69729782T2 (de) 1996-12-26 1997-12-24 Busarbiter

Country Status (4)

Country Link
US (2) US6070212A (de)
EP (1) EP0851360B1 (de)
JP (1) JPH10187600A (de)
DE (1) DE69729782T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3656370B2 (ja) * 1997-08-28 2005-06-08 セイコーエプソン株式会社 画像処理装置、情報処理装置およびプリンタ
JP2000134466A (ja) * 1998-10-21 2000-05-12 Murata Mach Ltd 画像処理装置
US6253269B1 (en) * 1998-12-22 2001-06-26 3Com Corporation Bus arbiter system and method for managing communication buses
US7248733B2 (en) * 1999-04-26 2007-07-24 Canon Kabushiki Kaisha Color-image processing apparatus and method, and storage medium
US6976108B2 (en) * 2001-01-31 2005-12-13 Samsung Electronics Co., Ltd. System on a chip having a system bus, an external bus, and a bus arbiter with programmable priorities for both buses, software, and method for assigning programmable priorities
US7917667B2 (en) * 2006-09-22 2011-03-29 Sony Computer Entertainment Inc. Methods and apparatus for allocating DMA activity between a plurality of entities
US8185672B2 (en) * 2011-01-14 2012-05-22 Texas Instruments Incorporated Transmission of data bursts on a constant data rate channel

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4292668A (en) * 1979-01-31 1981-09-29 Honeywell Information Systems Inc. Data processing system having data multiplex control bus cycle
JPS63140490A (ja) * 1986-12-03 1988-06-13 Sharp Corp ダイナミツクｒａｍ
US5345577A (en) * 1989-10-13 1994-09-06 Chips & Technologies, Inc. Dram refresh controller with improved bus arbitration scheme
JPH03254497A (ja) * 1990-03-05 1991-11-13 Mitsubishi Electric Corp マイクロコンピュータ
US5265231A (en) * 1991-02-08 1993-11-23 Thinking Machines Corporation Refresh control arrangement and a method for refreshing a plurality of random access memory banks in a memory system
US5307458A (en) * 1991-12-23 1994-04-26 Xerox Corporation Input/output coprocessor for printing machine
US5418920A (en) * 1992-04-30 1995-05-23 Alcatel Network Systems, Inc. Refresh control method and system including request and refresh counters and priority arbitration circuitry
US5467295A (en) * 1992-04-30 1995-11-14 Intel Corporation Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit
US5638529A (en) * 1992-08-24 1997-06-10 Intel Corporation Variable refresh intervals for system devices including setting the refresh interval to zero
US5682498A (en) * 1993-11-12 1997-10-28 Intel Corporation Computer system with dual ported memory controller and concurrent memory refresh
US5835737A (en) * 1996-05-10 1998-11-10 Apple Computer, Inc. Method and apparatus for arbitrating access to selected computer system devices

Also Published As

Publication number Publication date
EP0851360A3 (de) 1999-06-16
US6529981B1 (en) 2003-03-04
EP0851360A2 (de) 1998-07-01
JPH10187600A (ja) 1998-07-21
US6070212A (en) 2000-05-30
DE69729782T2 (de) 2005-07-07
EP0851360B1 (de) 2004-07-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition