DE69527365D1 - Hierarchische serielle busvorrichtung - Google Patents

Hierarchische serielle busvorrichtung

Info

Publication number
DE69527365D1
DE69527365D1 DE69527365T DE69527365T DE69527365D1 DE 69527365 D1 DE69527365 D1 DE 69527365D1 DE 69527365 T DE69527365 T DE 69527365T DE 69527365 T DE69527365 T DE 69527365T DE 69527365 D1 DE69527365 D1 DE 69527365D1
Authority
DE
Germany
Prior art keywords
serial bus
bus device
hierarchical serial
hierarchical
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69527365T
Other languages
English (en)
Other versions
DE69527365T2 (de
Inventor
Charles Morriss
Mckenzie Volk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE69527365D1 publication Critical patent/DE69527365D1/de
Publication of DE69527365T2 publication Critical patent/DE69527365T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)
DE69527365T 1994-10-31 1995-10-31 Hierarchische serielle busvorrichtung Expired - Lifetime DE69527365T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/332,337 US5621901A (en) 1994-10-31 1994-10-31 Method and apparatus for serial bus elements of an hierarchical serial bus assembly to electrically represent data and control states to each other
PCT/US1995/014245 WO1996013778A1 (en) 1994-10-31 1995-10-31 Hierarchical serial bus assembly

Publications (2)

Publication Number Publication Date
DE69527365D1 true DE69527365D1 (de) 2002-08-14
DE69527365T2 DE69527365T2 (de) 2003-03-27

Family

ID=23297779

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69527365T Expired - Lifetime DE69527365T2 (de) 1994-10-31 1995-10-31 Hierarchische serielle busvorrichtung

Country Status (6)

Country Link
US (1) US5621901A (de)
EP (1) EP0789880B1 (de)
AU (1) AU4100796A (de)
DE (1) DE69527365T2 (de)
HK (1) HK1002783A1 (de)
WO (1) WO1996013778A1 (de)

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US5623610A (en) 1994-10-31 1997-04-22 Intel Corporation System for assigning geographical addresses in a hierarchical serial bus by enabling upstream port and selectively enabling disabled ports at power on/reset
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US5991546A (en) * 1996-09-17 1999-11-23 Cmd Technology, Inc. System and method for interfacing manually controllable input devices to a universal computer bus system
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KR100211801B1 (ko) * 1997-03-12 1999-08-02 윤종용 Usb장치의 전원제어장치 및 제어방법
US6070211A (en) * 1997-06-11 2000-05-30 International Business Machines Corporation Driver/receiver circuitry for enhanced PCI bus with differential signaling
US6233611B1 (en) 1998-05-08 2001-05-15 Sony Corporation Media manager for controlling autonomous media devices within a network environment and managing the flow and format of data between the devices
US6009533A (en) * 1998-06-02 1999-12-28 Via-Cyrix, Inc. Speculative bus cycle acknowledge for 1/2X core/bus clocking
US6359951B1 (en) 1998-06-03 2002-03-19 Intel Corporation Method and apparatus for high speed signaling
US6438604B1 (en) 1998-10-05 2002-08-20 Canon Kabushiki Kaisha Digital video network interface
US7013354B1 (en) 1998-10-05 2006-03-14 Canon Kabushiki Kaisha Channel protocol for IEEE 1394 data transmission
US6253268B1 (en) 1999-01-15 2001-06-26 Telefonaktiebolaget L M Ericsson (Publ) Method and system for multiplexing a second interface on an I2C interface
US6546018B1 (en) 1999-05-10 2003-04-08 Intel Corporation Digital system having a peripheral bus structure with at least one store-and-forward segment
US6629186B1 (en) 1999-05-10 2003-09-30 Intel Corporation Bus controller and associated device drivers for use to control a peripheral bus having at least one store-and-forward segment
US6389501B1 (en) 1999-05-10 2002-05-14 Intel Corporation I/O peripheral device for use in a store-and-forward segment of a peripheral bus
US7359376B1 (en) 2000-11-20 2008-04-15 Thomson Licensing Serial compressed bus interface having a reduced pin count
WO2003009533A1 (fr) * 2001-07-11 2003-01-30 Fujitsu Limited Dispositif d'interface et procede de commande associe
US7466174B2 (en) 2006-03-31 2008-12-16 Intel Corporation Fast lock scheme for phase locked loops and delay locked loops
TWI444021B (zh) * 2007-09-17 2014-07-01 Htc Corp 解譯串列傳輸訊號之方法
US20090171163A1 (en) * 2007-12-31 2009-07-02 Mates John W Modular medical devices
EP3809610B1 (de) * 2018-07-11 2024-03-27 Huawei Technologies Co., Ltd. Vorrichtung, verfahren und system zur signalerzeugung

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Also Published As

Publication number Publication date
DE69527365T2 (de) 2003-03-27
AU4100796A (en) 1996-05-23
EP0789880B1 (de) 2002-07-10
EP0789880A4 (de) 1998-08-12
EP0789880A1 (de) 1997-08-20
WO1996013778A1 (en) 1996-05-09
US5621901A (en) 1997-04-15
HK1002783A1 (en) 1998-09-18

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