KR970072663A - Digital Noise Filter - Google Patents

Digital Noise Filter Download PDF

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Publication number
KR970072663A
KR970072663A KR1019960010584A KR19960010584A KR970072663A KR 970072663 A KR970072663 A KR 970072663A KR 1019960010584 A KR1019960010584 A KR 1019960010584A KR 19960010584 A KR19960010584 A KR 19960010584A KR 970072663 A KR970072663 A KR 970072663A
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KR
South Korea
Prior art keywords
gate
receiving
output
counting
signal
Prior art date
Application number
KR1019960010584A
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Korean (ko)
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KR100194672B1 (en
Inventor
김영기
Original Assignee
윤종용
삼성전자 주식회사
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Publication date
Application filed by 윤종용, 삼성전자 주식회사 filed Critical 윤종용
Priority to KR1019960010584A priority Critical patent/KR100194672B1/en
Priority to DE19712790A priority patent/DE19712790A1/en
Priority to CN97110309A priority patent/CN1110134C/en
Priority to JP9090449A priority patent/JPH1070444A/en
Publication of KR970072663A publication Critical patent/KR970072663A/en
Application granted granted Critical
Publication of KR100194672B1 publication Critical patent/KR100194672B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/08—Networks for phase shifting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0238—Measures concerning the arithmetic used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H21/00—Adaptive networks
    • H03H21/0012—Digital adaptive filters

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  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Noise Elimination (AREA)

Abstract

이 발명은 디지털 노이즈 필터에 관한 것으로, 디지털 신호를 입력받아, 업 또는 카운팅을 하기 위한 카운팅 수단과; 상기 카운팅 수단의 출력신호를 입력받아, 계수치가 일정치에 도달하면 출력을 내보내기 위한 출력 판단수단과; 상기 출력 판단수단내의 일부분 출력을 입력받고, 디지털입력신호와 클럭신호를 입력받아 상기 카운팅 수단의 카운팅동작을 개시 또는 중단하기 위한 상태천이 제어수단을 포함하여 구성되어, 적은 수의 플립플롭으로 폭이 긴 노이즈라도 쉽게 제거하며, 적은 비용으로 제작할 수 있는 잇점이 있는 디지털 노이즈 필터에 관한 것이다.The present invention relates to a digital noise filter, comprising: counting means for receiving a digital signal and performing up or counting; Output determination means for receiving an output signal of the counting means and outputting an output when the count value reaches a predetermined value; And a state transition control means for receiving a partial output of the output determination means and receiving a digital input signal and a clock signal to start or stop the counting operation of the counting means, The present invention relates to a digital noise filter having the advantage of being able to easily remove even long noise and to manufacture it at low cost.

Description

디지털 노이즈 필터Digital noise filter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제5도는 이 발명의 실시예에 따른 디지털 노이즈 필터의 기본원리의 상태천이도, 제6도는 이 발명의 실시예에 따른 디지털 노이즈 필터의 각 신호의 파형도.FIG. 5 is a state transition diagram of the basic principle of the digital noise filter according to the embodiment of the present invention; FIG. 6 is a waveform diagram of each signal of the digital noise filter according to the embodiment of the present invention;

Claims (4)

디지털신호를 입력받아, 업 또는 카운팅을 하기 위한 카운팅 수단과; 상기 카운팅 수단의 출력신호를 입력받아, 계수치가 일정치에 도달하면 출력을 내보내기 위한 출력 판단수단과; 상기 출력 판단수단내의 일부분 출력을 입력받고, 디지털 입력신호와 클럭신호를 입력받아 상기 카운팅 수단의 카운팅동작을 개시 또는 중단하기 위한 상태천이 제어수단을 포함하여 구성되어 짐을 특징으로 하는 디지털 노이즈 필터.Counting means for receiving a digital signal and counting up or counting; Output determination means for receiving an output signal of the counting means and outputting an output when the count value reaches a predetermined value; And a state transition control means for receiving a partial output from the output determination means and receiving or inputting a digital input signal and a clock signal to start or stop the counting operation of the counting means. 제1항에 있어서, 상기한 카운팅 수단은 계수보로서 업또는 다운 카운팅이 가능하며, 세 개의 출력을 이용하여 7개의 폭의 클럭신호에 해당하는 길이의 노이즈를 제거하는 것을 특징으로 하는 디지털 노이즈 필터.The digital noise filter according to claim 1, wherein the counting means counts up or down as counting beams, and removes noise having a length corresponding to a clock signal of seven widths using three outputs. . 제1항에 있어서, 상기한 출력 판단수단은, 상기 카운팅 수단은 세 개의 출력신호에 연결된 제1노아 게이트(79)와, 상기 카운팅수단의 세 개의 출력신호에 연결된 제1앤드 게이트(80)와, 상기 제1노아 게이트(80)에 세트 단자(set)가 연결되고, 상기 제1앤드게이트(80)에 리셋단자(reset)가 연결되어 있는 큐 플립플롭(81)으로 이루어지는 것을 특징으로 하는 디지털 노이즈 필터.3. The apparatus according to claim 1, wherein said output determining means comprises: a first NO gate (79) connected to three output signals; a first AND gate (80) connected to three output signals of said counting means; , And a cue flip flop (81) having a set terminal connected to the first Noah gate (80) and a reset terminal (reset) connected to the first end gate (80) Noise filter. 제1항에 있어서, 상기한 상태천이 제어수단은, 인버터(71)를 거친 입력신호(Vi)를 반전단자로 입력받고, 상기 제1앤드게이트(80)의 출력을 입력받는 제2앤드 게이트(75)와, 인버터(71)에 반전된 신호와 제1노아 게이트(79)의 출력 신호를 입력받는 제3앤드게이트(76)와, 상기 제2앤드 게이트(75)와 제3앤드 게이트(76)의 출력신호를 입력받아 논리연산한 값을 상기 계수부(73)의 클럭신호단자에 출력하는 제2노아 게이트(77)와, 상기 제2노아 게이트 (77)의 출력을 입력받고, 다른 한쪽으로 클럭신호(CLK)를 입력받아 제4앤드 게이트(78)로 이루어지는 것을 특징으로 하는 디지털 노이즈 필터.2. The semiconductor memory device according to claim 1, wherein said state transition control means comprises: an inverting terminal for receiving an input signal Vi through an inverter; a second AND gate for receiving an output of said first AND gate; A third AND gate 76 receiving a signal inverted by the inverter 71 and an output signal of the first NOR gate 79 and a second AND gate 75 and a third AND gate 76 A second N0 gate 77 for receiving the output signal of the second N0 gate 77 and outputting a value obtained by performing a logic operation on the output signal to the clock signal terminal of the counting unit 73, And a fourth AND gate (78) receiving the clock signal (CLK). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960010584A 1996-04-09 1996-04-09 Digital noise filter KR100194672B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019960010584A KR100194672B1 (en) 1996-04-09 1996-04-09 Digital noise filter
DE19712790A DE19712790A1 (en) 1996-04-09 1997-03-26 Digital noise filter for position control of robot used in die bonding
CN97110309A CN1110134C (en) 1996-04-09 1997-04-03 Digital noise-eliminating filter for lengthy noise
JP9090449A JPH1070444A (en) 1996-04-09 1997-04-09 Digital noise filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960010584A KR100194672B1 (en) 1996-04-09 1996-04-09 Digital noise filter

Publications (2)

Publication Number Publication Date
KR970072663A true KR970072663A (en) 1997-11-07
KR100194672B1 KR100194672B1 (en) 1999-06-15

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Country Status (4)

Country Link
JP (1) JPH1070444A (en)
KR (1) KR100194672B1 (en)
CN (1) CN1110134C (en)
DE (1) DE19712790A1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100548800B1 (en) * 1998-11-04 2006-04-21 페어차일드코리아반도체 주식회사 Digital filter
JP2006245977A (en) * 2005-03-03 2006-09-14 Fuji Xerox Co Ltd Pulse signal reproducing apparatus
JP5005275B2 (en) * 2006-07-03 2012-08-22 東芝機械株式会社 Digital filter device, phase detector, position detector, AD converter, zero cross detector, and digital filter program.
JP2008136085A (en) * 2006-11-29 2008-06-12 Renesas Technology Corp Toggle detection circuit
JP5123150B2 (en) * 2008-12-10 2013-01-16 株式会社東芝 Trigger signal detection device
JP5401180B2 (en) * 2009-06-17 2014-01-29 ルネサスエレクトロニクス株式会社 Digital noise filter circuit
JP5451309B2 (en) * 2009-10-27 2014-03-26 ルネサスエレクトロニクス株式会社 Noise removal circuit and semiconductor device provided with noise removal circuit
TWI443494B (en) * 2012-04-16 2014-07-01 M31 Technology Corp Clock Generation Method and System Using Pulse Wave Identification
CN107515566A (en) * 2016-06-15 2017-12-26 施耐德电气工业公司 Noise filter, noise filtering method and programmable logic controller (PLC)
JP2019097075A (en) 2017-11-24 2019-06-20 オムロン株式会社 Digital noise filter
CN112564693B (en) * 2020-12-18 2024-01-05 北京自动化控制设备研究所 Self-adaptive time keeping time service method
CN113904655B (en) * 2021-12-10 2022-02-25 极限人工智能有限公司 Filter circuit and medical 3D endoscope

Also Published As

Publication number Publication date
CN1110134C (en) 2003-05-28
DE19712790A1 (en) 1997-10-30
JPH1070444A (en) 1998-03-10
CN1169621A (en) 1998-01-07
KR100194672B1 (en) 1999-06-15

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