JP2006245977A - Pulse signal reproducing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To store an assert edge, even in a reproduction pulse in a pulse signal reproduction apparatus for removing noise contained in a pulse signal. <P>SOLUTION: The apparatus is provided with an RS-FF10 and a reset signal generator 20, provided with a borrow pulse generator 200 monitoring noise included in an input pulse signal. When the input pulse signal is asserted, the RS-FF10 is set and thereafter, a borrow pulse generator 200 starts monitoring of the presence/absence of the noise. When a noise removal object period passes without presence of the noise, the RS-FF10 is reset. The assert edge of a reproduction pulse is generated with the assert edge of the pulse signal as a start point, and the negate edge of the reproduction pulse is generated, after a period not shorter than a noise gate period passes without noise. Thus, even when the noise is superimposed to the pulse signal, the pulse signal from which the noise is removed can be reproduced, while keeping the occurrence timing of the assert edge. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a pulse signal reproducing apparatus. More specifically, the present invention relates to a technique for removing noise components contained in various pulse signals used in an electric circuit.

  In recent years, the circuit operation has been speeded up with the miniaturization of semiconductor processes, but the waveform dullness and ringing that occur when the input signal level transitions, which has not been a major problem, are mistakenly recognized as pulses. Has occurred. In addition, as the signal level is lowered, a phenomenon that the signal level is reversed due to externally mixed noise such as static electricity is likely to occur. For this reason, a technique for removing noise contained in the pulse signal is indispensable.

  As a technique for preventing a circuit malfunction due to such a waveform dullness, a method of shaping a dull waveform with a Schmitt trigger bus buffer is widely known. However, there is a problem that the waveform shaping effect cannot be obtained when ringing exceeding the Schmitt voltage is superimposed on the input signal. In addition to this, a technique of synchronizing the input signal with a clock and waiting for a time when the potential of a dull waveform is fixed or a time until ringing is stabilized before processing as a determined signal level is widely known.

  However, in this case, since the input signal is newly sampled with a clock that is asynchronous with the input signal, it cannot be used if the timing at which the input signal transitions is important, or the sampling frequency must be increased. As a result, a contradiction occurs such that the rising / falling of the waveform becomes too dull with respect to the sampling interval.

  Japanese Patent Application Laid-Open No. 2004-228688 aims to prevent malfunction caused by noise superimposed on an image data transfer start signal output from a printer, and to detect the image data transfer start signal with two pulses having different lengths. Thus, a mechanism for increasing resistance to noise is disclosed.

  Patent Document 2 discloses a malfunction caused by chattering noise superimposed on the rising edge and falling edge of a clock using a two-stage RS-FF and a delay circuit having a delay time corresponding to the chattering noise width to be removed. A mechanism for preventing this is disclosed.

Japanese Patent Laid-Open No. 7-210340 JP 2000-49577 A

  However, in the mechanism described in Patent Document 1, the image data start signal is delayed by a predetermined time, and the delayed image data start signal is latched by the edge of the image data start signal before the delay, so that the synchronization signal is generated. If there is noise such as chattering at the edge used to latch the image data start signal, correct processing cannot be performed.

  Further, in the mechanism described in Patent Document 2, the chattering noise is practically removed from both the rising edge and the falling edge of the input signal, which is considered to be almost complete in that sense. However, when only one of the rising edge and the falling edge of the input signal is effective, there is a problem that the circuit becomes redundant and excessive correction is performed.

  In addition, the delay signal of each edge is used for the set input and reset input, but usually the transition characteristics of each edge are different, resulting in a difference in the delay amount. The noise gate period must be set with the larger delay amount, and the degree of freedom of setting becomes narrower.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a mechanism that can remove noise with high accuracy while solving the problems of Patent Documents 1 and 2.

  The pulse signal reproducing device according to the present invention is a pulse signal reproducing device for removing noise contained in an input pulse signal, and a set input terminal for inputting a set signal for setting an output and a reset signal for resetting the output are input. A flip-flop having a reset input terminal (so-called RS flip-flop) and a noise monitoring unit that monitors noise included in the input pulse signal are provided.

  Here, when the input pulse signal is asserted, the flip-flop is set. After that, when the target period (also referred to as a noise gate period) for removing noise has passed without the presence of noise in the noise monitoring unit, the flip-flop is set. To reset.

  The claims are defined from one aspect of the relationship between the set and reset in the flip-flop and from the viewpoint of one polarity of the complementary type in the logic circuit. The relationship between the set and reset is reversed. It is also declared that a configuration of the above or a complementary configuration in which all logics are reversed is within the scope of the present invention.

  For example, when the input pulse signal is asserted, the reset signal is supplied to the reset input terminal to reset the flip-flop, and then the noise monitoring unit sets when the noise removal target period elapses without any noise. A configuration in which a flip-flop is set by supplying a signal to a set input terminal may be used.

  Also, for example, when the input pulse signal is negated, the flip-flop is reset, and after that, when a noise gate period for removing noise has passed without the presence of noise in the noise monitoring unit, the flip-flop is set. It is good.

  “Noise monitoring unit that monitors the noise contained in the input pulse signal” means that the wrong signal is not input to the set input terminal or reset input terminal of the flip-flop due to the noise contained in the input pulse signal. means.

  For example, even if an incorrect set signal is sequentially input to the set input terminal of the flip-flop due to noise included in the input pulse signal, an incorrect reset signal is input to the reset input terminal until the target period for eliminating noise elapses. Is prohibited.

  Or, even if an incorrect reset signal is sequentially input to the reset input terminal of the flip-flop due to noise included in the input pulse signal, the incorrect set signal is input to the set input terminal until the target period for eliminating the noise has elapsed. Is prohibited.

  The invention described in the dependent claims defines a further advantageous specific example of the pulse signal reproducing device according to the present invention.

  According to the present invention, an RS flip-flop and a noise monitoring unit that monitors noise included in the input pulse signal are provided, and when the input pulse signal is asserted (or negated), the flip-flop is set (or reset), Thereafter, when the noise removal target period has passed without the presence of noise, the flip-flop is reset (or set).

  As a result, the assertion edge (or negate edge) of the reproduction pulse is generated starting from the assertion edge (or negation edge) of the pulse signal, and the reproduction pulse negate edge (or assertion edge) is passed after the noise gate period has passed without noise. Therefore, even when noise is superimposed in the vicinity of the edge of the pulse signal, it is possible to reproduce the pulse signal from which the noise is removed while maintaining the generation timing of the assert edge (or negate edge). That is, even in the reproduction pulse, the assert edge (or negate edge) can be stored with high accuracy. As a result, it is possible to prevent malfunction of a circuit using pulses.

  In addition, since processing is performed by paying attention to the assert edge (or negate edge), unlike the mechanism described in Patent Document 2, it can be configured to focus only on one of the rising edge and falling edge of the input signal, Problems with the degree of freedom in setting the noise gate period due to the difference in delay due to the transition characteristics of each edge, or the circuit becomes redundant when only one of the rising edge and falling edge of the input signal is valid. It is possible to solve the problem of the mechanism described in Japanese Patent Laid-Open No. 2004-26853, such as a simple correction. Of course, when both edges are valid, it can be dealt with by processing each of them as an assert edge.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  The purpose of this embodiment is to reproduce with high accuracy a periodic pulse signal (hereinafter referred to as a periodic pulse) that includes an input noise component and has a meaning at an edge and a level that is basically meaningless. As described above, RS (reset / set) -FF (flip-flop), a clock signal generator that generates a clock signal that is asynchronous with the periodic pulse, and a counter that operates in synchronization with the generated clock signal Configure the device.

  As a configuration of the counter that defines the end timing of the active period of the reproduced pulse signal, a down counter may be used or an up counter may be used.

  Then, RS-FF is set at the asserted (active) edge of the input periodic pulse, and the reset timing of RS-FF is created by a counter.

  Hereinafter, each of the case where the up counter is used and the case where the down counter is used will be described in detail.

  The reset / set differs depending on whether the assert edge of the pulse signal to be processed is a falling edge, or conversely, the assert edge is a rising edge.

  In the present embodiment, for the purpose of reproducing the synchronization signal output from the printer engine with high accuracy, the RS (reset / set) -FF (flip-flop) and the synchronization signal are asynchronous with each other. The counter that operates in synchronization with the generated clock constitutes a synchronization signal reproducing unit. As the configuration of the counter, an up counter or a down counter may be used. Hereinafter, each of the case where the down counter is used and the case where the up counter is used will be described in detail.

  In the following description, when the pulse signal is active L, “N” is added to the beginning of the signal name. Similarly, for active L input terminals such as gates and FFs, “N” is added to the beginning of the terminal name.

  Further, in the following description, an active L synchronization signal (for example, an image data transfer start signal) output from the printer engine as a periodic pulse to be processed is meaningful only at the timing of transition from H level to L level. That is, a synchronization signal whose assert edge is a falling edge will be described as an example. In this case, the RS-FF is set (the non-inverted output is set to H level) at the asserted edge of the input synchronization signal NSYNCin, and the reset timing of the RS-FF is created by the counter.

<First Embodiment; Down Counter; Configuration>
FIG. 1 is a diagram illustrating a pulse signal reproducing device 1 according to the first embodiment. Here, FIG. 1A is a circuit block diagram showing the configuration of the pulse signal reproducing device 1 of the first embodiment, and FIG. 1B is loaded (for setting the noise gate period). It is a figure explaining how to give data.

  The first embodiment uses a down counter as a gate period for monitoring noise existing in the vicinity of the start and end of the active period, in particular, a counter that defines the end timing, and the peripheral timing of the count operation (this example) In this case, the setting range of the noise gate period for monitoring the noise is adjusted by adjusting (until the barrow pulse is output). Further, the down counter stop timing of the down counter is set to “0”. Further, the present invention is characterized in that a set priority type RS-FF is used.

  As shown in FIG. 1A, the pulse signal reproducing device 1 of the first embodiment receives a set-priority RS-FF 10 and an input synchronization signal NSYNCin (signal B) including a noise component. Inverting the logic, the inverter 12 that supplies the synchronization signal SYNCin (signal H) as a set signal to the set terminal S of the RS-FF 10, and the reset signal generation that supplies the reset signal (signal G) to the reset terminal R of the RS-FF 10 The unit 20 is provided. The reset signal generation unit 20 functions as a noise monitoring unit that monitors noise included in the input pulse signal.

  The reset signal generator 20 generates a borrow pulse Borrow (signal) based on an initial reset signal when power is turned on (hereinafter also referred to as a power-on reset signal NPRST; signal A) and a synchronization signal NSYNCin to be reproduced including an input noise component. A borrow pulse generator 200 for generating G) is included.

  The borrow pulse generation unit 200 includes a down counter 208 that down-counts an input clock signal CLK, and a count value setting unit 209 that sets an initial value to the data terminal Data of the down counter 208.

  In the down counter 208, a predetermined clock signal CLK is input to the clock terminal CK, predetermined data defining a noise gate period is set to the data terminal Data by the count value setting unit 209, and a power-on reset signal NPRST is set to the reset terminal NReset. (Signal A) is supplied, and a synchronization signal NSYNCin (signal B) to be reproduced is supplied to the load terminal NLoad.

  In such a configuration, data defining the noise gate period is set by the count value setting unit 209, the count operation is started from the set data, and the period until the borrow pulse Borrow (signal G) is output is determined as noise. This is the set width of the noise gate period for monitoring. Therefore, if the data value given by the count value setting unit 209 is adjusted, the set width of the noise gate period can be adjusted.

  Although not shown, the power-on reset signal NPRST (signal A) and the synchronization signal NSYNCin (signal B) may be supplied to each input terminal via a Schmitt trigger buffer as necessary.

  As the count value setting unit 209, a method of setting a variable value by a CPU or a feedback circuit, a method of setting a semi-fixed value by a dip switch or the like at the time of factory shipment or manually by a user, or fixed by a resistor Various configurations such as a method of setting a value can be employed.

  The down counter 208 is operated by a clock signal CLK that is asynchronous with the synchronization signal NSYNCin. At power-on, the counter value is cleared to an initial value “0” by a power-on reset signal NPRST (signal A) and a borrow pulse Borrow is output. When the synchronization signal NSYNCin is in the active period (L level in this example), the data value of the data terminal Data is loaded as a counter value.

  The down counter 208 basically loads predetermined data Dd to set the time to be measured when the synchronization signal NSYNCin is asserted, and the synchronization signal NSYNCin is negated and inactive (H level). The count down is performed until the count value becomes “0”. When the count value becomes “0”, the count operation is stopped, and at the same time, while the count value is “0”, a borrow pulse Borrow used as a signal for resetting the RS-FF 10 is output.

  By doing so, the pulse signal reproducing device 1 sets a noise gate period for monitoring noise existing near the end of the active period of the pulse signal to be reproduced (here, the synchronization signal NSYNCin), and After the pulse signal is negated, monitoring for the presence of noise is started. Then, noise removal processing is performed in the vicinity of the negate edge so that the noise present at the negate level within the set period is not included in the reproduction pulse (here, the synchronization signal NSYNCout).

  This setting also automatically sets the noise gate period to monitor the noise that exists in the vicinity of the start of the active period, and starts monitoring the presence or absence of noise after the pulse signal to be played is asserted. To do. Then, noise removal processing is performed in the vicinity of the assert edge so that noise existing at the assert level within the set period is not included in the reproduction pulse (here, the synchronization signal NSYNCout).

  Here, the count value setting unit 209 sets the noise gate period so that the time during which the down counter 208 counts down is sufficient for the noise included in the falling and rising edges of the synchronization signal NSYNCin to converge. A prescribed data value (hereinafter also referred to as noise gate data Dd) is set.

  The set input terminal S of the RS-FF 10 receives the synchronization signal SYNCin (signal H) logically inverted by the inverter 222, and the reset terminal R receives the borrow pulse Borrow (signal G) output from the borrow terminal Borrow of the down counter 208. Is entered. The pulse (signal E) output from the inverting output terminal NQ of the RS-FF 10 is used as the synchronization signal NSYNCout from which the noise component has been removed.

<First Embodiment; Down Counter; Operation>
FIG. 2 is a truth table (A) and a state transition diagram (B) for explaining the operation of the pulse signal reproducing device 1 of the first embodiment shown in FIG. 2A is a truth table for the RS-FF 10, and FIG. 2B is a state transition diagram showing an operation sequence of the down counter 208. FIG.

  FIG. 3 is a timing chart for explaining the operation of the pulse signal reproducing apparatus 1 of the first embodiment shown in FIG. Note that although there is a difference in the time until each output value is determined in various logic circuits, for the sake of convenience, the description will be made on the assumption that the RS-FF 10 has a shorter output delay than the down counter 208. To do.

  First, as shown in FIG. 2A, the RS-FF 10 is a set priority type RS-FF (the significance of which will be described later). For example, when the L level is input to both the set terminal S and the reset terminal R, the non-inverted output terminal Q and the inverted output terminal NQ hold the previous output value. When the reset terminal R is at the L level and the H level is input to the set terminal S, the non-inverted output terminal Q is set to the H level and the inverted output terminal NQ is set to the L level. If the H level is input to the reset terminal R when the set terminal S is at the L level, the non-inverted output terminal Q is reset to the L level and the inverted output terminal NQ is reset to the H level. Also, if H level is input to both the set terminal S and the reset terminal R, since it is set priority type, the non-inverted output terminal Q is set to H level and the inverted output terminal NQ is set to L level. To do.

  The pulse signal reproducing apparatus 1 starts normal operation after the power-on reset signal NPRST becomes H level. For example, in the initial state, the count value of the down counter 208 is indefinite, the counter is operated by the clock input, and the output value of the borrow terminal Borrow is also undefined.

  Here, when the power-on reset signal NPRST becomes L level when the synchronization signal NSYNCin is at H level (before t10), the set terminal S of the RS-FF 10 is L level and the reset terminal NReset of the down counter 208 is L level. Thus, the down counter 208 is reset (the count is stopped in FIG. 2B), the count value of the down counter 208 becomes “0”, and the borrow pulse Borrow is output. As a result, the reset terminal R of the RS-FF 10 becomes H level, the RS-FF 10 is reset, the RS-FF 10 is in a reset state, that is, the non-inverting output terminal Q becomes L level, and the inverting output terminal NQ becomes H level. Before that, if the RS-FF 10 is in a reset state, the state is maintained.

  If the power-on reset signal NPRST returns to H level when the synchronization signal NSYNCin is at H level (t10), the set terminal S of the RS-FF 10 is at L level and the count value of the down counter 208 remains “0”. Therefore, the reset state (the count stop of FIG. 2B) is maintained, and the borrow pulse Borrow is continuously output from the down counter 208. As a result, the reset terminal R of the RS-FF 10 maintains the H level. The FF 10 maintains the reset state.

  Next, the falling transition period of the active-low synchronization signal NSYNCin will be described. First, when the power-on reset signal NPRST is at the H level (after t10), when the synchronization signal NSYNCin transitions to the L level (t15), the falling edge is inverted by the inverter 12, and the rising edge is set to RS-FF10. The signal is input to the terminal S, and the set terminal S is set to the H level.

  At this time, since the borrow pulse Borrow supplied to the lit terminal R of the RS-FF 10 is at the H level, the output is indefinite if it is a normal RS-FF for which priority is not defined. Therefore, the RS-FF 10 is set, so that the non-inverted output terminal Q becomes H level and the inverted output terminal NQ becomes L level (t16).

  As a result, an assert edge of the synchronization signal NSYNCout is generated. That is, when the synchronization signal SYNCin is input to the set terminal S of the RS-FF 10, and the synchronization signal NSYNCin exceeds the input threshold voltage of the RS-FF 10, the non-inverted output Q of the RS-FF 10 is set to H level. The inverted output NQ of the corresponding RS-FF 10 automatically becomes L level.

  Further, since the load signal NLoad of the down counter 208 becomes L level by the transition of the synchronization signal NSYNCin to L level (t15), the down counter 208 loads the noise gate data Dd supplied to the data terminal Data. (The count value load in FIG. 2B) is entered. Thereby, the borrow pulse Borrow (signal G) transits to the L level, and this is supplied to the reset terminal R of the RS-FF 10 (t17). At this time, since the set terminal S of the RS-FF 10 is at the H level, the set state is continuously maintained.

  While the synchronization signal NSYNCin is at the L level, the down counter 208 keeps loading the noise gate data Dd supplied to the data terminal Data (the count value loading in FIG. 2B). RS-FF10 also maintains the set state.

  Next, when the synchronization signal NSYNCin includes noise (particularly chattering noise generated near its falling edge) and the synchronization signal NSYNCin becomes H level without maintaining the original L level period (t20), the synchronization signal NSYNCin is down. The counter 208 starts a down count operation from the noise gate data Dd (t22; Count Down State in FIG. 2B).

  Here, when the synchronization signal NSYNCin returns to the original L level before the count value of the down counter 208 becomes “0” (t30), the H level is supplied to the set terminal S of the RS-FF 10 to set it. However, since the load terminal Nload of the down counter 208 is at the L level, the noise gate data Dd supplied to the data terminal Data is loaded again (t32; count value load in FIG. 2B).

  As a result, the down counter 208 stops outputting the borrow pulse Borrow and supplies the L level to the reset terminal R of the RS-FF 10, so that the set terminal S becomes the H level and the reset terminal R becomes the L level. However, before that, the set terminal S and the reset terminal R are in a state where there is no change in the L level, and in fact, the previous set state is maintained and no change occurs. .

  Also, when the synchronization signal NSYNCin includes the following noise and the H level → L level is repeated before the count value of the down counter 208 becomes “0”, the same operation as the above-described t20 to t32 is performed. repeat.

  Since the active low pulse signal is handled, the H level (negate level) period of the noise component existing at the start of the active period is for monitoring the noise existing near the end of the active low period, which will be described later. It is almost impossible to become longer than the set width of the noise gate period. Therefore, it is possible to reliably remove noise existing in the vicinity of the start of the active period of the pulse signal to be reproduced (here, the synchronization signal NSYNCin).

  Next, the rising transition period of the active-low synchronization signal NSYNCin will be described. When the original L level period (assertion level period) of the synchronization signal NSYNCin has almost passed and the synchronization signal NSYNCin becomes H level, the synchronization signal NSYNCin contains noise (particularly chattering noise generated near its rising edge). (T35 to t47), and when the H level → L level is repeated before the count value of the down counter 208 becomes “0”, the same operation as the above-described t20 to t32 is repeated.

  Thereafter, when the H level of the synchronization signal NSYNCin continues stably and the count value of the down counter 208 becomes “0” (t50), the down counter 208 stops counting and outputs a borrow pulse Borrow. , RS-FF10 is reset to the reset terminal R with the set terminal S at the L level, the non-inverted output terminal Q is reset to the L level, and the inverted output terminal NQ is reset to the H level (t51). . Thereby, a negated edge of the synchronization signal NSYNCout is generated.

  When the synchronization signal NSYNCin newly shifts to the L level after the RS-FF 10 is reset, the same operation as the above-described t15 to t51 is repeated.

  As a result, the synchronization signal NSYNCout having an active period from t16 to t51 (L level period in this example) is output to the inverting output terminal NQ of the RS-FF10. Since active low pulse signals are handled, the H level period of the noise component present at the end of the active period is the same as the H level of the original inactive period that is not a noise component.

  However, the set width of the noise gate period (t45 to t50 in this example) for monitoring the noise existing near the end of the active low period is set to be somewhat longer than the assumed H level period of the noise component. Thus, the H level period of the noise component can be prevented from appearing in the synchronization signal NSYNCout, and the noise present near the end of the active period of the pulse signal to be reproduced (here, the synchronization signal NSYNCin) is surely removed. can do.

  The period width from t16 to t51 is influenced by the number of pulse noises present near the negated edge (rising edge in the above example) of the synchronization signal NSYNCin, but defines the assert edge (falling edge in the above example). Since t16 is one-to-one with the assertion edge (falling edge in the above example) t15 of the synchronization signal NSYNCin, the repetition cycle of the assertion edge of the synchronization signal NSYNCin can be maintained in the synchronization signal NSYNCout. .

  Therefore, even when noise is included in a pulse signal whose assert edge is a falling edge, which is meaningful only at the timing of transition from the H level to the L level, it can be reproduced while maintaining its periodicity. That is, the waveform of the output pulse changes at the beginning of the change of the waveform of the input periodic pulse, and noise can be removed from the input periodic pulse without changing the phase, frequency, and duty of the periodic pulse.

  In the above description, the periodic pulse whose assertion edge is the falling edge is processed, but within the range allowed by the noise gate period, that is, the interval between the first assertion edge and the second assertion edge that follows it is set. If it is longer than the noise gate period, the above-described noise removal effect can be enjoyed, and non-periodic pulses having no periodicity can be processed.

  As described above, according to the pulse signal reproducing device 1 of the first embodiment, the set signal is set to the set priority type RS-FF 10 using the assert edge of the pulse signal (synchronization signal NSYNCin in the above example) as a starting point. By supplying and setting to the terminal S, an assert edge of the reproduction pulse is generated, and after the inactive (negated) period after the active (asserted) period elapses more than the noise gate period, the reset signal is set priority type RS− The negated edge of the reproduction pulse is generated by supplying the reset input terminal R of the FF 10 for resetting.

  Thereby, even when noise is superimposed on the pulse signal, it is possible to reproduce the pulse signal from which noise has been removed while maintaining the assertion edge generation timing (repetition period in the case of a periodic pulse). As a result, malfunction of the circuit using the synchronization signal NSYNCout can be prevented. For example, even if noise is included in the image data transfer start signal, a synchronization signal can be accurately generated without being affected by the noise, and malfunction of other circuits using the synchronization signal can be prevented.

  Further, since the progress of the noise removal target period is measured using a counter, there is an advantage that the presence or absence of noise included in the pulse signal can be monitored with a very simple configuration.

  In addition, since the pulse signal is reproduced by controlling the set input and the reset input of the RS-FF, there is an advantage that noise included in the pulse signal can be removed with a very simple configuration.

  Further, the pulse signal reproducing device 1 having such a noise removing function can be easily realized by using only a logic circuit. Therefore, it can be easily incorporated into an ASIC (Application Specific IC).

  Also, since the count value setting unit 209 that sets the noise removal target period using the data terminal Data of the down counter 208 is provided, the noise gate period can be easily adjusted by the value set at the data terminal Data of the down counter 208 can do. Therefore, since the time for removing chattering noise of the input pulse can be set and changed according to the situation, noise removal can be realized regardless of the frequency of the pulse, and it can be easily applied to any system.

  Further, when the down counter 208 is used, there is an advantage that the method of giving the data value defining the noise gate period is easy for the user to handle. This is because, as shown in FIG. 1B, in the noise gate period Tn when the down counter 208 is used, the counter value becomes “0” from the data value Dd set at the data terminal Data of the down counter 208. This is because it is equal to the value obtained by multiplying the data value Dd by one period T0 of the count clock.

  That is, when the noise gate period is set by using the down counter 208 until the borrow pulse Borrow is output, the user can directly use the value Dd obtained by dividing the noise gate period Tn by one period T0 of the count clock as the down counter. It may be set to 208 data terminals Data.

<First Embodiment; About RS-FF>
FIG. 4 is a diagram for explaining the significance of replacing the RS-FF 10 with the set priority type RS-FF in the basic form of the first embodiment described above. Of course, the assert edge is a falling edge.

  It is the transition period at the fall of the active-low synchronization signal NSYNCin that is related to the setting priority RS-FF. First, when the count value becomes “0”, the down counter 208 stops the count operation and outputs a borrow pulse Borrow, that is, sets the signal G to the H level (t50). At substantially the same time, the RS-FF 10 is reset, and the inverted output terminal NQ of the RS-FF 10 transitions to the H level (t51). Since the count operation is stopped while the count value is “0”, the borrow pulse Borrow continues to be output and the signal G maintains the H level.

  When returning to the next falling transition period, the synchronization signal NSYNCin is asserted (t15), the load terminal NLoad of the down counter 208 becomes L level, and the noise gate data Dd is loaded into the down counter 208, whereby the borrow pulse Borrow ( The signal G) is negated (becomes L level) (t16). In this case, after the synchronization signal NSYNCin is asserted (t15) and until the borrow pulse Borrow is negated and becomes L level (t16), the RS-FF 10 is in a state where both the set terminal S and the reset terminal R are asserted. It becomes.

  Here, the synchronization signal NSYNCin to be processed has an assert edge that is a falling edge, that is, the synchronization signal NSYNCin has a meaning as a falling edge. Therefore, an assert edge of the synchronization signal NSYNCout (a falling edge in this example) ) Must be one-to-one with the assertion edge (falling edge in this example) of the synchronization signal NSYNCin.

  In addition, the timing at which the synchronization signal NSYNCout is asserted is as similar as possible to the timing at which the synchronization signal NSYNCin is asserted. It is.

  This is because if all control in the device is performed based on the synchronization signal NSYNCin, there will be no problem even if there is a time difference between the timings of the assertion edges of the synchronization signal NSYNCin and the synchronization signal NSYNCout. In such a case, such a case is rare, and there are also cases where control is performed on the basis of a pulse different from the synchronization signal NSYNCin (hereinafter referred to as a heterogeneous pulse group). In this case, if a time difference occurs between these different kinds of pulse groups and the synchronization signal NSYNCout, normal operation cannot be guaranteed for the entire target device equipped with the pulse signal reproducing device 1.

  Therefore, it is desirable to immediately drop the synchronization signal NSYNCout when the assertion edge (falling edge in this example) of the synchronization signal NSYNCin occurs. For this purpose, the inverted output terminal NQ of the RS-FF 10 immediately becomes L level. Thus, it is desired to set the RS-FF 10, and the RS-FF 10 should be set priority type.

  That is, in a state in which the H level of the borrow pulse Borrow is supplied to the lit terminal R of the RS-FF 10, the synchronization signal SYNCin is input to the set terminal S of the RS-FF 10 (t15), so that the RS-FF 10 is immediately turned on. The set state is set, and the non-inverted output Q of the RS-FF 10 is set to the H level (t16a).

  As a result, the time difference between the timings at which the assertion edges of the synchronization signal NSYNCin and the synchronization signal NSYNCout are generated can be reduced. Even in this case, as can be seen from the figure, there is a slight time difference Δta (= t16a−t15) between the timing of generation of the assertion edge of the synchronization signal NSYNCin (t15) due to gate delay or the like.

  On the other hand, when the RS-FF 10 is set to the reset priority type, the inverted output terminal NQ of the RS-FF 10 becomes H level while the borrow pulse Borrow is at H level, and the borrow pulse Borrow transitions to L level (t17). Is set (t16b), and after the synchronization signal SYNCin is asserted (t15), the inverting output terminal NQ of the RS-FF 10 becomes L level (t16b), and a large time difference Δtb (= t16b-t15) Will occur. A large time difference Δ (= t16b−t16a) occurs between the set priority type and the set priority type.

<Problems of set priority type RS-FF>
FIG. 5 and FIG. 6 are diagrams for explaining problems when the set-priority RS-FF 10 is used. In the above description, it has been explained that the use of the set priority type RS-FF 10 can reduce the time difference between the generation timings of the assert edges of the synchronization signal NSYNCin and the synchronization signal NSYNCout. Various problems arise when the RS-FF 10 is built.

  For example, as shown in the circuit diagram of FIG. 5A, a normal (hereinafter referred to as “normal type”) RS-FF 11 having no priority is used simultaneously with the set input terminal S and the reset input terminal R. It is conceivable to provide a priority circuit 30 that prevents the H level from being input (specifically, the set signal side is given priority).

  For example, in the example shown in the figure, by providing a priority circuit 30 including an inverter 32 and an AND gate 34 on the input side of a normal type RS-FF 11 composed of two NOR gates 11a and 11b, RS-FF10 is comprised.

  The set signal S is input to the set input Sin of the priority circuit 30, and is input as it is to the set input terminal S1 of the normal type RS-FF 11 (one input terminal of the NOR gate 11a) via the output Sout. It is also input to the inverter 32 and logically inverted. The set signal NS logically inverted by the inverter 32 is input to one input terminal of the AND gate 34. The reset signal R is input to the reset input Rin of the priority circuit 30 and input to the other input terminal of the AND gate 34.

  According to such a configuration of the prioritization circuit 30, as shown in the truth table shown in FIG. 5B, the AND gate 34 sets the set signal S to the L level even if the reset signal R is at the H level. Only when the reset signal R is valid. That is, when both the set signal S and the reset signal R are at the H level, the reset signal R is invalidated, and the set signal S is prioritized as the set output Sout and the reset output Rout of the priority circuit 30.

  The reset output Rout in which the set signal S side is prioritized by the AND gate 34 is input to the reset input terminal R1 of the normal type RS-FF 11 (one input terminal of the NOR gate 11b). As a result, even when the normal type RS-FF 11 is used, when both the set signal S and the reset signal R are at the H level, the set signal S is preferential, and as a whole, the set state is set. RS-FF10 can be configured.

  That is, when the set input S1 and the reset input R1 are both at the H level, the output of the normal type RS-FF 11 becomes indefinite, but by providing the priority circuit 30 on the input side, the set input S1 Even when both of the reset inputs R become H level, the set input S1 is H and the reset input R1 is L. Therefore, the non-inverted output Q is H, the inverted output NQ is L, and the output becomes unstable. Can be resolved.

  However, in reality, it seems to be no problem at first glance. This is because, assuming an actual operation, when the reset input R is at the H level, for example, as in the operation timing shown in FIG. 5C, the set input S may transition from the L level to the H level. obtain.

  In this case, as the reset output Rout of the priority circuit 30 that gives priority to the set signal side, after the set input S transitions from the L level to the H level (t10), the reset output Rout changes from the H level to the L level. By the transition to the level (t12), there is a slight time difference Δta (= t12−t10) due to the presence of the gate delay caused by the inverter 32 and the AND gate 34.

  For this reason, as the normal type RS-FF 11, both the set input S 1 and the reset input R 1 become H level by the delay time Δta of the priority circuit 30, and as a result, the delay amount in the normal type RS-FF 11. Even if is ignored, an indefinite output is output during the period from t10 to t12 (hatched portion).

  In order to solve this problem, in order to correct the time difference Δta (= t12−t10) generated in the priority circuit 30, for example, as shown in the circuit diagram of FIG. 6A, the set input Sin and the set output Sout It is conceivable to provide a delay circuit 36 between them. As the delay circuit 36, for example, various configurations such as a configuration using a delay by a gate circuit, a configuration using a counter, and an analog circuit configuration such as a glass delay element (Delay Line) can be adopted. .

  In this case, as in the operation timing shown in FIG. 6B, the time difference Δtb (= t14−t10) between the set input Sin and the set output Sout generated by the delay circuit 36 is different between the inverter 32 and the AND gate 34. By performing time delay processing so as to be equal to or greater than the generated time difference Δta (= t12−t10), an indefinite output can be prevented.

  However, when the delay circuit 36 is provided, a new problem occurs. For example, even when the delay in the normal RS-FF 11 is ignored, the outputs Q and NQ of the normal RS-FF 11 are delayed by the time difference Δtb (= t14−t10) by the delay circuit 36. As a result, when used as a noise removal circuit for the synchronization signal NSYNCin, the timing for generating the assertion edge of the synchronization signal NSYNCout is significantly delayed from the timing for generating the assertion edge of the synchronization signal NSYNCin. As a result, normal operation cannot be guaranteed.

  Further, when a counter is used for the delay circuit 36, the rising edge of the set input is not stored. In order to solve this problem, it is conceivable to adopt an analog circuit configuration such as a glass delay element. However, in this case, there is a problem that the affinity with a digital circuit (such as ASIC) is lowered.

  Here, in the first embodiment, the reason why the set priority type RS-FF 10 is originally adopted is that the H level is simultaneously input to the set input S1 and the reset input R1 of the normal type RS-FF11. Because. In other words, if the H level is simultaneously input to the set input S1 and the reset input R1 of the normal RS-FF 11 by using a technique other than providing the delay circuit 36 in the priority circuit 30. It is considered that the above-mentioned problems can be solved. Hereinafter, another embodiment from this viewpoint will be described.

Second Embodiment; Down Counter; Modification 1
7 and 8 are diagrams for explaining a modification 1 (referred to as a second embodiment) of the pulse signal reproducing device 1 of the first embodiment. Here, FIG. 7 is a timing chart for explaining the cause of the timing when the set signal and the reset signal are asserted simultaneously in the first embodiment, and FIG. 8 is a timing chart for explaining a technique for solving the problem. It is.

  The second embodiment is not limited to the set priority type RS-FF (that is, the set priority type RS-FF 10) by preventing the set signal and the reset signal from being asserted at the same time. Instead, a normal type RS-FF11 is used). Specifically, in the first embodiment, the downcount stop timing of the down counter 208 is set to “0”. However, in the second embodiment, the downcount stop timing of the down counter 208 is set to other than “0”. It has the characteristics.

  Here, a case where a 4-bit counter is used as the down counter 208 will be described. In this case, the decimal number “−1” is “Fh” in the hexa data (indicated by h). Further, it is assumed that the value loaded as noise gate data Dd into the down counter 208 is “Fh”. Of course, the assert edge is a falling edge.

  First, referring to FIG. 7, in the first embodiment, the cause of the timing at which the set signal and the reset signal are asserted simultaneously is confirmed. 7 shows that the synchronization signal SYNCin (set input S for RS-FF10) is clearly shown, the load data is clearly shown, and the indefinite period of the synchronization signal NSYNCout with respect to the operation timing shown in FIG. The only difference is that the (hatched part) is clearly indicated.

  The down counter 208 outputs a borrow pulse Borrow when the count value becomes “0”, that is, sets the signal G to the H level and stops the count operation (for example, t10 to t17). The H level of the borrow pulse Borrow is supplied to the reset input terminal R of the set priority type RS-FF 10. During this time, when the synchronization signal NSYNCin is asserted (for example, t15), the synchronization signal SYNCin (= signal H) logically inverted by the inverter 12 is supplied to the set input terminal S of the RS-FF 10, so that the synchronization signal NSYNCin Almost simultaneously with the assertion, the RS-FF 10 is reset, and its inverted output terminal NQ attempts to transition to the H level.

  On the other hand, when the synchronization signal NSYNCin is asserted (t15), the load terminal NLoad of the down counter 208 also becomes L level, and the noise gate data Dd (= Fh) is loaded into the down counter 208, thereby negating the borrow pulse Borrow. (L level) (t17).

  In this case, since the down counter 208 is loaded after the synchronization signal NSYNCin is asserted, the RS-FF10 is between the assertion of the synchronization signal NSYNCin and the borrow pulse Borrow being negated to the L level (t15 to t17). Is in a state where both the set terminal S and the reset terminal R are asserted.

  When the normal RS-FF 11 is used as the RS-FF without using the set priority type or the reset priority type, it is not known what the output of the RS-FF will be (output indefinite state). In order to solve this problem, as described above, a circuit that prevents both the set terminal S1 and the reset terminal R1 of the normal RS-FF 11 from being asserted (for example, FIG. 5A). Or the prioritization circuit 30 in FIG. 6A needs to be added.

<How to solve problems>
As can be seen from the above, in the first embodiment, the set terminal S and the reset terminal R of the RS-FF are both asserted because the count value is “0” and the count operation of the down counter 208 is performed. It can be considered that the synchronization signal NSYNCin is asserted while the H level is output from the borrow terminal Borrow. While the circuit configuration and operation are very simple, such as stopping the count operation when the count value is “0”, the set terminal S and the reset terminal R of the RS-FF are both asserted when the pulse signal is reproduced. There is an inconvenience.

  Therefore, if the synchronization signal NSYNCin is asserted in such a state that the H level is not output from the borrow terminal Borrow, both the set terminal and the reset terminal of the RS-FF are prevented from being asserted. be able to.

  FIG. 8 shows an example of a solution technique from this viewpoint. In this example, the downcount stop timing of the downcounter 208 is not “0” but a decimal number “−1”.

  Here, a case where a 4-bit counter is used as the down counter 208 will be described. In this case, the decimal number “−1” is “Fh” in the hexa data (indicated by h). Further, it is assumed that the value loaded as noise gate data Dd into the down counter 208 is “9h”. Of course, the assert edge is a falling edge.

  The down counter 208 sets the borrow terminal Borrow to H level when the count value becomes “0”, but continues without stopping the count operation. When the count value becomes “Fh”, the borrow terminal Borrow is set to L level. That is, the signal G is set to L level and the counting operation is stopped (t12). The L level of the borrow pulse Borrow is supplied to the reset input terminal R1 of the normal RS-FF11.

  During this time, when the synchronization signal NSYNCin is asserted (for example, t15), the synchronization signal SYNCin (= H level of the signal H) logically inverted by the inverter 12 is supplied to the set input terminal S1 of the normal type RS-FF11. . At this time, since the reset input terminal R1 of the normal type RS-FF 11 is at the L level, the normal type RS-FF 11 is reset almost simultaneously with the assertion of the synchronization signal NSYNCin, and its inverted output terminal NQ transitions to the H level. (T16). As a result, an assert edge of the synchronization signal NSYNCout is generated.

  In other words, when the synchronization signal NSYNCin is asserted in the transition period of the falling edge of the active-low synchronization signal NSYNCin, it is possible to avoid asserting the set input and the reset input of the normal type RS-FF 11 at the same time. Further, the synchronization signal NSYNCout is asserted almost simultaneously with the assertion of the synchronization signal NSYNCin.

  On the other hand, during the rising transition period of the active low synchronization signal NSYNCin, the H level of the synchronization signal NSYNCin continues stably, and when the count value of the down counter 208 becomes “0” (t50), the down counter 208 The borrow pulse Borrow is output, that is, the signal G is set to the H level, but the count operation is continued without stopping, and when the count value becomes “Fh”, the borrow terminal Borrow is set to the L level, that is, the signal G is set to the L level. The count operation is stopped (t52). The L level of the borrow pulse Borrow is supplied to the reset input terminal R1 of the normal RS-FF11.

  Here, when the borrow pulse Borrow is outputted from the down counter 208, the set signal S1 of the normal type RS-FF 11 is supplied with the synchronization signal SYNCin (= L level of the signal H) logically inverted by the inverter 12. Therefore, in the normal type RS-FF 11, the H level is input to the reset terminal R1 with the set terminal S1 at the L level, the non-inverted output terminal Q is set to the L level, and the inverted output terminal NQ is set to the H level. It is reset (t51). Thereby, a negated edge of the synchronization signal NSYNCout is generated.

  That is, in the second embodiment in which the downcount stop timing of the downcounter 208 is “−1”, the borrow pulse Borrow is output during the period from t50 to t52, and the time counted by the downcounter 208 is the negation time of the synchronization signal NSYNCin. By setting a short time with respect to t45 to t60, it is possible to avoid that the set input and the reset input of the normal RS-FF 11 are asserted at the same time even in the transition period of the rising edge of the active-low synchronization signal NSYNCin. .

  Even when the set priority type or the reset priority type is not used as the RS-FF, both the set terminal S1 and the reset terminal R1 of the normal type RS-FF 11 are asserted without adding a circuit. Can be surely prevented. Although the synchronization signal NSYNCout is negated with a delay of the noise gate period from the negation of the synchronization signal NSYNCin, the output does not become unstable.

<Third Embodiment; Down Counter; Configuration of Modification Example 2>
FIG. 9 and FIG. 10 are diagrams for explaining a modification 2 (referred to as the third embodiment) of the pulse signal reproducing device 1 of the first embodiment. Here, FIG. 9 is a circuit block diagram showing the configuration of the pulse signal reproducing device of the third embodiment, and FIG. 10 is a timing chart for explaining the operation of the pulse signal reproducing device of the third embodiment.

  The third embodiment is characterized in that a down counter is used as a counter that defines the end timing of the active period of the pulse signal to be reproduced (here, the synchronization signal NSYNCin). Also, the downcount stop timing of the downcounter is not particularly defined. Further, the present invention is characterized in that a normal RS-FF is used as the RS-FF.

  The biggest feature point is that the load timing of the down counter is defined by the output of the RS-FF. Specifically, when the input pulse signal is at the assert level and when the RS-FF is in the reset state, noise is generated. The gate data is fetched into the data input terminal of the counter. Hereinafter, this point will be specifically described.

  As shown in FIG. 9, the pulse signal regeneration device 1 according to the third embodiment loads the down counter 208 in order to define the load timing of the down counter by the output of the RS-FF with respect to the configuration of the first embodiment. A NOR gate 22 is provided on the input side of the terminal NLload to form the reset signal generation unit 20, and the pulse (signal E) output from the inverting output terminal NQ of the normal type RS-FF 11 is synchronized with noise components removed. Used as signal NSYNCout.

  The reset signal generation unit 20 also includes an inverter 24 that logically inverts the power-on reset signal NPRST (signal A), a power-on reset signal PRST (signal C) that is logically inverted by the inverter 24, and a barrow output (signal) of the down counter 208. And an OR gate 28 that takes the logical sum of G) and supplies the logical ring output (signal D) to the reset terminal R1 of the normal type RS-FF11.

  In the NOR gate 22, the synchronization signal SYNCin logically inverted by the inverter 12 is input to one input terminal, and the pulse (signal E) output from the inverted output terminal NQ of the normal RS-FF 11 is input to the other input terminal. The logical sum output (signal F) is supplied to the load terminal NLoad of the down counter 208.

  In the down counter 208, when L level is simultaneously input to the reset terminal NReset and the load terminal NLoad, the reset is given priority.

<Third Embodiment; Operation>
FIG. 10 is a timing chart for explaining the operation of the pulse signal reproducing apparatus 1 of the third embodiment shown in FIG.

  When the synchronization signal NSYNCin is at the H level and the power-on reset signal NPRST is at the L level, the normal RS-FF 11 is reset because the set input terminal S1 is set to the L level and the reset input terminal is set to the H level. And the inverted output terminal becomes H level.

  Further, since the L level of the power-on reset signal NPRST is supplied to the reset terminal Nreset of the down counter 208, the reset is prioritized regardless of the state of the load terminal NLoad (signal F). As a result, the count value of the down counter 208 becomes “0”, and the down counter 208 outputs a borrow pulse Borrow (H level). This information is supplied to one input terminal of the OR gate 28. Since the H level obtained by logically inverting the power-on reset signal NPRST by the inverter 24 is already supplied to the other input terminal, the normal type is supplied. No change occurs for RS-FF11.

  At this time, the H level information of the inverted output terminal of the normal type RS-FF 11 is input to the load terminal NLoad of the down counter 208 as the L level via the NOR gate 22. However, at this time, the L level of the power-on reset signal NPRST is supplied to the reset terminal Nreset of the down counter 208, and resetting is given priority to the down counter 208, so the count value of the down counter 208 is “0”. As a result of the continuous output of the borrow pulse Borrow from the down counter 208, the normal RS-FF 11 maintains the set terminal S1 at the L level and the reset terminal R1 at the H level. -FF11 maintains the reset state.

  When the normal RS-FF 11 is in the reset state and the synchronization signal NSYNCin is at the H level, when the power-on reset signal NPRST returns to the H level (t10), the reset of the down counter 208 is released, and the normal type The loading of the down counter 208 by the reset state of the RS-FF 11 becomes effective. As a result, the down counter 208 loads the noise gate data Dd supplied to the data terminal Data (t12). As a result, the borrow pulse Borrow (signal G) transitions to the L level and is supplied to the reset terminal R of the RS-FF 10 (t13). At this time, since the set terminal S1 of the normal type RS-FF 11 is at the L level, the reset state is continuously maintained.

  Next, the falling transition period of the active-low synchronization signal NSYNCin will be described. First, when the power-on reset signal NPRST is at the H level (after t12), when the synchronization signal NSYNCin transits to the L level (t15), the falling edge is inverted by the inverter 12, and the rising edge is the normal RS−. The signal is input to the set terminal S1 of the FF 11, and the set terminal S1 is set to the H level.

  At this time, since the borrow pulse Borrow supplied to the reset terminal R1 of the normal type RS-FF 11 is at the L level, the normal type RS-FF 11 is set, the non-inverted output terminal Q is set to the H level, and the inverted output terminal NQ becomes L level (t16). As a result, an assert edge of the synchronization signal NSYNCout is generated.

  In other words, when the synchronization signal NSYNCin is asserted in the transition period of the falling edge of the active-low synchronization signal NSYNCin, it is possible to avoid asserting the set input and the reset input of the normal type RS-FF 11 at the same time. Further, the synchronization signal NSYNCout is asserted almost simultaneously with the assertion of the synchronization signal NSYNCin.

  Further, while the synchronization signal NSYNCin is at the L level, the information is supplied to the load terminal NLoad of the down counter 208 via the NOR gate 22, so that the inverted output (signal E) of the RS-FF 11 is at the L level. In addition, the down counter 208 maintains a state where the noise gate data Dd supplied to the data terminal Data is continuously loaded. The normal type RS-FF 11 also maintains the set state.

  Next, when the synchronization signal NSYNCin includes noise (particularly chattering noise generated near its falling edge) and the synchronization signal NSYNCin becomes H level without maintaining the original L level period (t20), the synchronization signal NSYNCin is down. The counter 208 starts a down count operation from the noise gate data Dd (t23). At this time, the normal type RS-FF 11 maintains the set state because both the set terminal S1 and the reset terminal R1 are at the L level.

  Here, if the synchronization signal NSYNCin returns to the original L level before the count value of the down counter 208 becomes “0” (t30), the load terminal Nload of the down counter 208 becomes L level and is supplied to the data terminal Data. The noise gate data Dd to be loaded is loaded again (t32).

  Since the down counter 208 continues to maintain the borrow pulse terminal Borrow at the L level, the down counter 208 continues to supply the L level to the reset terminal R1 of the normal RS-FF 11. In the normal type RS-FF 11, the set terminal S1 is at the H level and the reset terminal R is at the L level, but before that, the set terminal S1 and the reset terminal R1 are in the state of no change in the L level. In addition, the previous set state is maintained and no change occurs.

  Also, when the synchronization signal NSYNCin includes the following noise and the H level → L level is repeated before the count value of the down counter 208 becomes “0”, the same operation as the above-described t20 to t32 is performed. repeat.

  Next, the rising transition period of the active-low synchronization signal NSYNCin will be described. When the original L level period of the synchronization signal NSYNCin has almost passed and the synchronization signal NSYNCin becomes H level, the synchronization signal NSYNCin contains noise (particularly chattering noise generated near the rising edge) (t35 to 35). t46) Even when the H level → L level is repeated before the count value of the down counter 208 becomes “0”, the same operation as the above-described t20 to t32 is repeated.

  Thereafter, when the H level of the synchronization signal NSYNCin continues stably and the count value of the down counter 208 becomes “0” (t50), the down counter 208 outputs a borrow pulse Borrow, that is, the signal G is set to the H level. To do.

  Here, when the borrow pulse Borrow is outputted from the down counter 208, the set signal S1 of the normal type RS-FF 11 is supplied with the synchronization signal SYNCin (= L level of the signal H) logically inverted by the inverter 12. Therefore, in the normal type RS-FF 11, the H level is input to the reset terminal R1 with the set terminal S1 at the L level, the non-inverted output terminal Q is set to the L level, and the inverted output terminal NQ is set to the H level. It is reset (t51). Thereby, a negated edge of the synchronization signal NSYNCout is generated.

  Further, the H level information of the inverting output terminal NQ is used to set the down counter 208 to the load state via the NOR gate 22. In the illustrated example, since the delay time in the gate circuit is intentionally long, at t52, the counter value exceeds “0” and counts down to “Fh = −1”, and then the load data Dd = 9 is set. Loading. In actual use, the down counter 208 may be configured to count down to “0” and stop, or the count operation may be continued as it is and the count down may be continued recursively.

  Thus, also in the third embodiment, the synchronization signal NSYNCout can be generated at substantially the same timing as in the second embodiment. In other words, if the borrow pulse Borrow becomes active at t50 and the time counted by the down counter 208 is set shorter than the negation times t45 to t60 of the synchronization signal NSYNCin, even in the transition period of the rising edge of the active-low synchronization signal NSYNCin, It can be avoided that the set input and the reset input of the normal type RS-FF 11 are asserted simultaneously.

  Even when the set priority type or the reset priority type is not used as the RS-FF, both the set terminal S1 and the reset terminal R1 of the normal type RS-FF 11 are asserted without adding a circuit. Can be surely prevented. Although the synchronization signal NSYNCout is negated with a delay of the noise gate period from the negation of the synchronization signal NSYNCin, the output does not become unstable.

<Fourth Embodiment; Up Counter; Configuration>
FIG. 11 is a diagram for explaining the pulse signal reproducing device 1 of the fourth embodiment. Here, FIG. 11A is a circuit block diagram showing the configuration of the pulse signal reproducing device 1 of the fourth embodiment, and FIG. 11B is loaded (for setting the noise gate period). It is a figure explaining how to give data.

  The fourth embodiment is different from the configuration of the first embodiment in that a gate period for monitoring noise existing near the start or end of the active period of the pulse signal to be reproduced (here, the synchronization signal NSYNCin), In particular, the counter is characterized in that it is modified to use an up-counter as a counter that defines the end timing. This will be specifically described below.

  As shown in FIG. 11A, the pulse signal regeneration device 1 of the fourth embodiment replaces the borrow pulse generator 200 in the pulse signal regeneration device 1 of the first embodiment shown in FIG. It has changed.

  The carry pulse generator 240 replaces the down counter 208 with the up counter 248 in the pulse signal regeneration device 1 of the first embodiment shown in FIG. In the up-counter 248, a predetermined clock signal CLK is input to the clock terminal CK, predetermined data (noise gate data) Du defining a noise gate period is set to the data terminal Data by the count value setting unit 209, and the preset terminal NPreset Is supplied with a power-on reset signal NPRST (signal A) so that full data (here, Fh) is output, and a synchronization signal NSYNCin (signal B) to be reproduced is supplied to the load terminal NLoad. It has become. The preset of the up counter 248 is preferably clock synchronization.

  The up counter 248 counts up while the synchronization signal NSYNCin is at the H level until the count value becomes “full data = Fh”. When the count value reaches “full data”, the count operation is stopped, and at the same time, while the count value is “full data = Fh”, a carry pulse Carry used as a signal for resetting the RS-FF 10 (signal g) Is output. The generated carry pulse Carry is supplied to the reset terminal R of the RS-FF 10.

  The count value setting unit 209 sets data Du for defining the noise gate period, starts the count operation from the set data Du, and monitors the noise during the period until the carry pulse Carry (signal g) is output. The set width of the noise gate period. Therefore, if the value of the data Du given by the count value setting unit 209 is adjusted, the setting range of the noise gate period can be adjusted.

<Fourth Embodiment; Up Counter; Operation>
FIG. 12 is a timing chart for explaining the operation of the pulse signal reproducing device 1 according to the fourth embodiment shown in FIG. Although a detailed description is omitted, the main difference from the first embodiment shown in FIG. 3 is that the up counter 248 is first set to “full data = Fh” by a power-on reset signal NPRST (signal A) Is a point (before t10) at which the carry pulse Carry (signal g) is output.

  The falling transition period of the active-low synchronization signal NSYNCin is substantially the same as in the first embodiment. When the power-on reset signal NPRST is at the H level (after t10), the synchronization signal NSYNCin transitions to the L level. (T15), the falling edge is inverted by the inverter 12, the rising edge is input to the set terminal S of the RS-FF 10, and the set terminal S is set to the H level.

  At this time, since the carry pulse Carry (signal g) supplied to the lit terminal R of the RS-FF 10 is at the H level, the output is indefinite if it is a normal RS-FF for which priority is not defined. In this embodiment, since the set-priority RS-FF 10 is used, the RS-FF 10 is set, the non-inverting output terminal Q becomes H level, and the inverting output terminal NQ becomes L level (t16).

  As a result, an assert edge of the synchronization signal NSYNCout is generated. Further, it is possible to reliably remove noise existing in the vicinity of the start of the active period of the pulse signal to be reproduced (here, the synchronization signal NSYNCin).

  The second major difference is that the H level of the synchronization signal NSYNCin continues stably during the transition period of the rising edge of the active-low synchronization signal NSYNCin, and the count value of the up counter 248 becomes “Fh” (t50). The up-counter 248 stops the counting operation and outputs a carry pulse Carry at the same time. Thereby, in the RS-FF 10, the H level is input to the reset terminal R in a state where the set terminal S is at the L level, the non-inverted output terminal Q is reset to the L level, and the inverted output terminal NQ is reset to the H level ( t51). Thereby, a negated edge of the synchronization signal NSYNCout is generated. Further, it is possible to reliably remove noise existing in the vicinity of the end of the active period of the pulse signal to be reproduced (here, the synchronization signal NSYNCin).

  As described above, even if the configuration of the first embodiment using the down counter 208 is modified using the up counter 248, the assertion edge of the reproduction pulse starts from the assertion edge of the pulse signal (synchronization signal NSYNCin in the above example). Can generate the negate edge of the playback pulse after the inactive (negated) period after the active (asserted) period exceeds the noise gate period, even if noise is superimposed on the pulse signal While maintaining the edge generation timing (repetition period in the case of a periodic pulse), it is possible to reproduce the pulse signal from which noise has been removed, and as a result, it is possible to prevent malfunction of the circuit using the synchronization signal NSYNCout. The same effects as those of the first embodiment can be enjoyed.

  In addition, when the general-purpose logic IC is used, the up counter has more parts, which is advantageous in terms of availability and price, and has an advantage of using the fourth embodiment. For example, focusing on Texas Instruments' 74 series logic IC counters, only up counters or counters with up / down switching functions are available, but there are no counters with only down functions. This embodiment using a counter is advantageous.

  However, as shown in FIG. 11B, when the noise gate period is set by using the up counter 248 until the carry pulse Carry is output, how to give the data value Du that defines the noise gate period However, it becomes difficult for the user to handle. This is because the noise gate period Tn when the up counter 248 is used is a period from the data value Du set at the data terminal Data of the up counter 248 until the counter value becomes “full data”. It is not equal to the value Du multiplied by one period T0 of the count clock. Specifically, a value ΔT obtained by subtracting the noise gate period Tn from the total period Tfull when the full data is counted by the count clock CLK of one cycle T0 is obtained, and this value ΔT is divided by one cycle T0 of the count clock. Du may be set to the data terminal Data of the up counter 248.

  In the description of the fourth embodiment, a modification to the first embodiment is shown. However, the present invention is not limited to this, and similarly to the second and third embodiments, a pulse signal to be reproduced (here, The up-counter can be modified to use a gate period for monitoring noise existing in the vicinity of the start or end of the active period of the synchronization signal NSYNCin), particularly as a counter that defines the end timing.

<Fifth Embodiment; Up Counter + Comparator; Configuration>
FIG. 13 is a diagram for explaining the pulse signal reproducing device 1 of the fifth embodiment. Here, FIG. 13A is a circuit block diagram showing the configuration of the pulse signal reproducing device 1 of the fifth embodiment, and FIGS. 13B and 13C are data for setting the noise gate period. It is a figure explaining how to give.

  In the fifth embodiment, the count operation is stopped by continuing to clear (reset) the counter using the comparison result in the comparator (comparator), and the noise is monitored by adjusting the stop timing. It is characterized in that it is configured to adjust the set width of the noise gate period. Hereinafter, a modification to the fourth embodiment will be specifically described.

  As shown in FIG. 13, the pulse signal reproduction device 1 of the fifth embodiment logically inverts the normal RS-FF 11 and the synchronization signal NSYNCin (signal B) to be reproduced including the input noise component. An inverter 12 that supplies a synchronization signal SYNCin (signal H) as a set signal to the set terminal S1 of the normal type RS-FF 11, and a reset signal that supplies a reset signal (signal G) to the reset terminal R1 of the normal type RS-FF 11 The generation unit 20 is provided, and a pulse (signal E) output from the inverting output terminal NQ of the normal type RS-FF 11 is used as a synchronization signal NSYNCout from which a noise component is removed.

  The reset signal generation unit 20 functions as a noise monitoring unit that monitors noise included in the input pulse signal. The reset signal generation unit 20 includes a logic comparison unit 250 that logically compares the count value and the data Du that defines the noise gate period, instead of the carry pulse generation unit 240.

  In addition to the count value setting unit 209 and the up counter 248, the logic comparison unit 250 logically outputs the count output (signal K) of the up counter 248 and the data Du that defines the noise gate period set by the count value setting unit 209. For comparison, a comparator 252 for outputting a comparison coincidence output (signal L) from an output terminal Comp is provided.

  The reset signal generator 20 also includes an inverter 24 that logically inverts the power-on reset signal NPRST (signal A), a synchronization signal SYNCin (signal H) that is logically inverted by the inverter 12, and a power-on reset that is logically inverted by the inverter 24. And a NOR gate 26 for taking the logical sum of the signal PRST (signal C) and the inverted output (signal E) of the normal type RS-FF 11.

  The reset signal generator 20 takes a logical sum of the power-on reset signal PRST (signal C) logically inverted by the inverter 24 and the comparison coincidence output (signal L) from the comparator 252, and outputs the logical sum output (signal M). ) As a reset signal to the reset terminal R1 of the normal type RS-FF11.

  In the up counter 248, a predetermined clock signal CLK is inputted to the clock terminal CK, the logical sum output (signal J) from the NOR gate 26 is supplied to the clear terminal NClear, and the logical sum output (signal J) is at the L level. The count value is set to the initial state (in this example, cleared to “0”), the input pulse signal is at the negate level, the normal RS-FF 11 is in the set state, and the logical sum output (signal J) is at the H level. During this period, the count operation is started from the count value = zero, and the count value is output from the output terminal (Count Out) to one input terminal A of the comparator 252. The clearing of the up counter 248 is preferably clock synchronous.

  In such a configuration, the count value setting unit 209 continuously sets the data Du defining the noise gate period to one input terminal B of the comparator 252, and the up counter 248 counts from count value = zero. The period until the comparison coincidence output (signal L) is obtained by the comparator 252 is set as the set width of the noise gate period for monitoring noise. Therefore, if the value of the data Du given by the count value setting unit 209 is adjusted, the setting range of the noise gate period can be adjusted.

  Here, the count value setting unit 209 has a noise gate period so that the time that the up-counter 248 counts up is sufficient for the noise included in the falling and rising edges of the synchronization signal NSYNCin to converge. Is set to a data value (noise gate data Du) that defines.

  When viewed as a whole, basically, when the synchronization signal NSYNCin is asserted, the up counter 248 is cleared to set the time to be measured, and the count value is set while the synchronization signal NSYNCin is negated and inactive (H level). Is counted up to the data Du set by the count value setting unit 209. Then, at the same time when the count value coincides with the data Du, a comparison coincidence output (signal L) used as a signal for resetting the normal type RS-FF 11 is output.

  By doing so, also in the pulse signal reproduction device 1 of the fifth embodiment, the noise gate period for monitoring the noise existing near the end of the active period of the pulse signal to be reproduced (here, the synchronization signal NSYNCin) And monitoring for the presence or absence of noise is started after the pulse signal to be reproduced is negated. Then, noise removal processing is performed in the vicinity of the negate edge so that the noise present at the negate level within the set period is not included in the reproduction pulse (here, the synchronization signal NSYNCout).

  This setting also automatically sets the noise gate period to monitor the noise that exists in the vicinity of the start of the active period, and starts monitoring the presence or absence of noise after the pulse signal to be played is asserted. To do. Then, noise removal processing is performed in the vicinity of the assert edge so that noise existing at the assert level within the set period is not included in the reproduction pulse (here, the synchronization signal NSYNCout).

<Fifth Embodiment; Up Counter + Comparator; Operation>
FIG. 14 is a timing chart for explaining the operation of the pulse signal reproducing device 1 of the fifth embodiment shown in FIG.

  When the power-on reset signal NPRST (signal A) becomes active and becomes L level (before t10), the power-on reset signal NPRST (signal A) is supplied to the clear terminal NClear of the up counter 248 via the inverter 24 and the NOR gate 26. Then, the up counter 248 stops the count operation and outputs the count value = 0 from the output terminal (Count Out) to one input terminal A of the comparator 252.

  Therefore, the comparison match output (signal L) by the comparator 252 becomes inactive = L level, and this is input to one input terminal of the OR gate 28. At this time, the power-on reset signal PRST (signal J) is input to one input terminal of the OR gate 28. As a result, the normal-type RS− is received by the power-on reset signal NPRST (signal A). The FF 11 is reset, the non-inverting output terminal Q becomes L level, and the inverting output terminal NQ becomes H level.

At this time, the H level of the inverting output terminal NQ is supplied to the clear terminal NClear of the up counter 248 via the NOR gate 26, but the up counter 248 has already been cleared by the power-on reset signal NPRST (signal A). There is no change.
When the power-on reset signal NPRST (signal A) is canceled and becomes H level (t10 to t15), both input terminals of the OR gate 28 become L level, so that the normal type RS-FF 11 has the set terminal S1 and reset. The terminal R1 becomes L level and there is no change.

  The falling transition period of the active-low synchronization signal NSYNCin is substantially the same as that of the fourth embodiment. When the power-on reset signal NPRST is at the H level and the synchronization signal NSYNCin transitions to the L level (t15), The falling edge is inverted by the inverter 12, the rising edge is input to the set terminal S1 of the normal type RS-FF 11, and the set terminal S1 is set to the H level.

  At this time, since the OR output (signal M) by the OR gate 28 supplied to the lit terminal R1 of the normal type RS-FF 11 is at the L level, the normal type RS-FF 11 is set and the non-inverted output terminal Q becomes H level and the inverted output terminal NQ becomes L level (t16). As a result, an assert edge of the synchronization signal NSYNCout is generated.

  At this time, since the inverted output terminal NQ becomes L level, the clearing of the up counter 248 via the NOR gate 26 is about to be canceled, but when the synchronization signal NSYNCin transits to L level (t15), the inverter 12 Thus, the logic-inverted H level is supplied to the clear terminal NClear of the up-counter 248 via the NOR gate 26, so that the up-counter 248 remains cleared and has no change. This state continues while the synchronization signal NSYNCin is at L level.

  Next, when the synchronization signal NSYNCin includes noise (particularly chattering noise generated in the vicinity of its falling edge) and the synchronization signal NSYNCin becomes H level without maintaining the original L level period (t20), NOR. Since the output of the gate 26 (signal J) becomes H level and the clearing of the up counter 248 is released (t21), the up counter 248 starts the up count operation from the count value = 0 (t23). At this time, the comparison coincidence output (signal L) by the comparator 252 remains inactive = L level, and this is input to one input terminal of the OR gate 28. Therefore, the normal RS-FF 11 has a set terminal. Both S1 and the reset terminal R1 become L level, the set state which is the previous state is maintained, and no change occurs.

  Here, when the synchronization signal NSYNCin returns to the original L level before the count value of the up counter 248 reaches the data value Du set at the input terminal B of the comparator 252, (t30), the falling edge becomes the inverter. 12, the rising edge is input to the set terminal S1 of the normal RS-FF 11, and the set terminal S1 is set to the H level.

  At this time, the H level logically inverted by the inverter 12 is supplied as the L level to the clear terminal NClear of the up counter 248 via the NOR gate 26 (t31), so the up counter 248 is cleared (t33). . At this time, the comparison coincidence output (signal L) from the comparator 252 remains inactive = L level, and this is input to one input terminal of the OR gate 28. Therefore, the normal RS-FF 11 has the set terminal S1. Is at the H level and the reset terminal R1 is at the L level, and is in the set state, but before that, the set terminal S1 and the reset terminal R1 are in the state in which there is no change in the L level. Maintained, and no change occurs. This state continues while the synchronization signal NSYNCin is at L level.

  Further, when the synchronization signal NSYNCin includes the following noise and the H level → L level is repeated before the count value of the up counter 248 reaches the data value Du set at the input terminal B of the comparator 252. The operation similar to that at t20 to t33 described above is repeated.

  Since the active low pulse signal is handled, the H level period of the noise component existing at the start of the active period is a noise gate period for monitoring noise existing near the end of the active low period, which will be described later. Longer than the set width is hardly conceivable. Therefore, it is possible to reliably remove noise existing in the vicinity of the start of the active period of the pulse signal to be reproduced (here, the synchronization signal NSYNCin).

  Next, the rising transition period of the active-low synchronization signal NSYNCin will be described. When the original L level period of the synchronization signal NSYNCin has almost passed and the synchronization signal NSYNCin becomes H level, the synchronization signal NSYNCin contains noise (particularly chattering noise generated near the rising edge) (t35 to 35). t46) Even when the H level → L level is repeated before the count value of the up counter 248 reaches the data value Du set at the input terminal B of the comparator 252, the same operation as the above-described t20 to t33 is repeated. .

  Thereafter, when the H level of the synchronization signal NSYNCin continues stably, the count value of the up counter 248 matches the data value Du (“9” in this example) set at the input terminal B of the comparator 252 (t50). The comparator 252 sets the comparison coincidence output (signal L) to the H level (S51 to t53).

  At this time, in the normal type RS-FF 11, since the set terminal S1 is at the L level, when the comparison coincidence output (signal L) becomes the H level, this is input to one input terminal of the OR gate 28. In the type RS-FF11, the H level is input to the reset terminal R1 with the set terminal S1 at the L level, the non-inverted output terminal Q is reset to the L level, and the inverted output terminal NQ is reset to the H level (t52). ). Thereby, a negated edge of the synchronization signal NSYNCout is generated.

  Further, the H level information of the inverting output terminal NQ is used for setting the up counter 248 to the clear state via the NOR gate 26. In the illustrated example, since the delay time in the gate circuit is intentionally long, the counter value exceeds the data value Du (in this example, “9”) at t53 and has counted up to “Ah” and thereafter. Cleared (t54). In actual use, the up counter 248 may be configured to count up to the data value Du and stop, or the count operation may be continued as it is and the count up may be continued recursively.

  When the synchronization signal NSYNCin newly shifts to the L level after the RS-FF 10 is reset, the same operation as the above-described t15 to t51 is repeated.

  As a result, the synchronization signal NSYNCout having an active period (L level period in this example) from t16 to t52 is output to the inverting output terminal NQ of the normal type RS-FF11. Since active low pulse signals are handled, the H level period of the noise component present at the end of the active period is the same as the H level of the original inactive period that is not a noise component.

  However, the set width of the noise gate period (t45 to t50 in this example) for monitoring the noise existing near the end of the active low period is set to be somewhat longer than the assumed H level period of the noise component. Thus, the H level period of the noise component can be prevented from appearing in the synchronization signal NSYNCout, and the noise present near the end of the active period of the pulse signal to be reproduced (here, the synchronization signal NSYNCin) is surely removed. can do.

  Note that the period width from t16 to t52 is affected by the number of noises present at the negated edge (rising edge in the above example) of the synchronization signal NSYNCin as in the first embodiment, but is asserted edge (rising edge in the above example). Since t16 defining the falling edge is one-to-one with the assertion edge (falling edge in the above example) t15 of the synchronization signal NSYNCin, the repetition cycle of the assertion edge possessed by the synchronization signal NSYNCin is defined in the synchronization signal NSYNCout. Can also be maintained.

  Therefore, even when noise is included in a pulse signal whose assert edge is a falling edge, which is meaningful only at the timing of transition from the H level to the L level, it can be reproduced while maintaining its periodicity. That is, the waveform of the output pulse changes at the beginning of the change of the waveform of the input periodic pulse, and noise can be removed from the input periodic pulse without changing the phase, frequency, and duty of the periodic pulse.

  As described above, in the fifth embodiment configured to adjust the setting width of the noise gate period for monitoring noise using the comparator 252, the assert edge of the pulse signal (synchronization signal NSYNCin in the above example) is also provided. As a starting point, the assertion edge of the regenerative pulse can be generated, and after the inactive (negate) period after the active (assertion) period has passed the noise gate period or longer, the negate edge of the regenerative pulse can be generated. Even when the signal is superimposed, the pulse signal from which noise has been removed can be reproduced while maintaining the assertion edge generation timing (repetition period in the case of a periodic pulse). As a result, the synchronization signal NSYNCout is used. The same effects as those of the first to fourth embodiments can be obtained, such as prevention of malfunction of the circuit to be performed.

  Also in the fifth embodiment, the synchronization signal NSYNCout can be generated at substantially the same timing as in the second embodiment. In other words, the comparison coincidence output (signal L) becomes active at t50 (t51 because there is actually a gate delay), and the time counted by the up counter 248 is set shorter than the negation times t45 to t60 of the synchronization signal NSYNCin. For example, it is possible to avoid asserting the set input and the reset input of the normal type RS-FF 11 at the rising transition period of the active-low synchronization signal NSYNCin.

  Even when the set priority type or the reset priority type is not used as the RS-FF, both the set terminal S1 and the reset terminal R1 of the normal type RS-FF 11 are asserted without adding a circuit. Can be surely prevented. Although the synchronization signal NSYNCout is negated with a delay of the noise gate period from the negation of the synchronization signal NSYNCin, the output does not become unstable.

  Also, unlike the fourth embodiment, the count value is cleared and then counted up, and the noise gate period is set by using the time until the comparison match output (signal L) is obtained by the comparator 252. Although the counter 248 is used, as in the first embodiment, the method of giving the data value Du that defines the noise gate period is easy for the user to handle.

  This is because, as shown in FIG. 13B, in the noise gate period Tn in the fifth embodiment, the counter value is the data value Du set at one input terminal B of the comparator 252 from “zero = 0”. (Because the comparison coincidence output (signal L) becomes active H), which is equal to the value obtained by multiplying the data value Du by one period T0 of the count clock. That is, in the fifth embodiment, the user may set a value Du obtained by dividing the noise gate period Tn by one period T0 of the count clock to one input terminal B of the da comparator 252 as it is.

  In addition, as in the fourth embodiment, when the general-purpose logic IC is used, the up counter has more parts, which is advantageous in terms of availability and price. Therefore, when the circuit is configured using the general-purpose logic IC, the fifth embodiment in which the up counter and the comparator are combined can achieve both parts availability and ease of handling by the user.

  However, since it is necessary for the comparator 252 to generate a comparison coincidence output (signal L) that defines the end of the noise gate period, there is a disadvantage that the circuit configuration becomes complicated.

  In the description of the fifth embodiment, a gate period for monitoring noise existing near the start and end of the active period of the pulse signal to be reproduced (here, the synchronization signal NSYNCin), particularly the end timing, is defined. Although a modification to the fourth embodiment using an up counter as a counter is shown, the present invention is not limited to this, and the present invention can be similarly applied to a case where a down counter is used.

  When the down counter is used, it is difficult for the user to provide the data value Dd that defines the noise gate period. This is because when a down counter is used as shown in FIG. 13C, the count value is preset to full data rather than being cleared to “0” in order to set the count value to the initial state. Then, when the input pulse signal is at the negate level and the normal type RS-FF 11 is in the set state, it counts down from the full data until the comparison coincidence output (signal L) is obtained by the comparator 252. Sets the noise gate period.

  For this reason, the noise gate period Tn is a period from when the counter value reaches the data value Dd set at the data terminal Data of the down counter, which is equal to the data value Dd and one cycle T0 of the count clock. It is not equal to the value multiplied by. Specifically, a value ΔT obtained by subtracting the noise gate period Tn from the total period Tfull when the full data is counted by the count clock CLK of one cycle T0 is obtained, and this value ΔT is divided by one cycle T0 of the count clock. It is necessary to set Dd to the data terminal Data of the down counter.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above-described embodiment, the pulse signal whose falling edge is the assert edge has been described as an example. However, the present invention can be similarly applied to a pulse signal whose rising edge is the assert edge by reversing the logical configuration. In the case of a pulse signal in which both edges have a valid meaning, the processing is performed with each edge as an assert edge, and one pulse is reproduced based on the asserted edge of the reproduction pulse reproduced at each edge. Can cope.

  In the above embodiment, when the input pulse signal is asserted, a noise gate (noise removal target) period is set, and monitoring for the presence or absence of noise is started, thereby causing chattering that occurs in the vicinity of the assert edge. However, the period for monitoring the noise may be set to other periods. For example, monitoring of the presence or absence of noise may be started after the input pulse signal is negated. Of course, as in Patent Document 1, it may be set to remove noise generated in the middle of two adjacent assert edges.

  Further, in the above embodiment, the edge of the synchronization signal is detected, and it is configured not to malfunction due to noise generated in the vicinity of the edge. However, if the interval of the synchronization signal is known in advance, It is possible to adopt a configuration using

  For example, the RS-FF is set at the assertion edge of the synchronization signal, and at the same time, the time until immediately before the next synchronization signal is input is counted by the counter. The counter is configured to start counting from the asserted edge part of the synchronization signal, so that it resets to the reset input terminal of the flip-flop until it reaches the next asserted edge as the target period for removing noise after the asserted edge. The input of a signal is prohibited, and monitoring of the presence or absence of noise in the meantime is started. In this case, it is possible to prevent malfunction due to noise included in the edge portion of the synchronization signal and at the same time to prevent malfunction due to inversion of the signal level resulting from noise superimposed on the synchronization signal from the outside.

  Moreover, in the said embodiment, although RS-FF itself was used, what is necessary is just a flip-flop which has the reset input terminal into which the signal which resets the set input terminal and the output which inputs the signal which sets an output is input, You may make it operate | move as RS-FF substantially using JK-FF etc.

  In the second, third, and fifth embodiments, the normal type RS-FF 11 having no priority is used. However, this is not essential, and the set priority type RS-FF 10 is used. But there is no inconvenience.

  Moreover, in the said embodiment, although the signal G used in order to reset RS-FF10 was produced | generated using the counter circuit, whether noise gate period passes without noise existing in an input pulse signal? It is only necessary that the signal G can be generated by monitoring the above, and other configurations can be adopted. As an example, a timer circuit using a mono multivibrator can be used. Alternatively, the monitoring is not limited to a hardware configuration such as a counter circuit or a timer circuit, and may be monitored by software. Since the hardware configuration is suitable for high-speed operation, it is suitable for processing a high-speed pulse with a short repetition period. On the other hand, since the software configuration is highly scalable, it is suitable for a case where a low-speed pulse having a long repetition cycle is to be processed.

It is a figure explaining the pulse signal reproducing | regenerating apparatus 1 of 1st Embodiment. It is a figure explaining operation | movement of the pulse signal reproducing | regenerating apparatus of 1st Embodiment. It is a timing chart explaining operation | movement of the pulse signal reproducing | regenerating apparatus of 1st Embodiment. In the basic form of 1st Embodiment, it is a figure explaining the significance of having changed RS-FF into set priority type RS-FF. It is FIG. (1) explaining the problem in the case of using a set priority type RS-FF. It is FIG. (2) explaining the problem in the case of using set priority type RS-FF. It is FIG. (1) explaining operation | movement of the pulse signal reproducing | regenerating apparatus of 2nd Embodiment. It is FIG. (2) explaining operation | movement of the pulse signal reproducing | regenerating apparatus of 2nd Embodiment. It is a circuit block diagram which shows the structure of the pulse signal reproducing | regenerating apparatus of 3rd Embodiment. It is a timing chart explaining operation | movement of the pulse signal reproducing | regenerating apparatus of 3rd Embodiment. It is a figure explaining the pulse signal reproducing | regenerating apparatus of 4th Embodiment. It is a timing chart explaining operation | movement of the pulse signal reproducing | regenerating apparatus of 4th Embodiment. It is a figure explaining the pulse signal reproducing | regenerating apparatus of 5th Embodiment. It is a timing chart explaining operation | movement of the pulse signal reproducing | regenerating apparatus of 5th Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Pulse signal reproduction | regeneration apparatus, 10 ... Set priority type RS-FF, 11 ... Normal type RS-FF, 20 ... Reset signal generation part, 30 ... Prioritization circuit, 200 ... Borrow pulse generation part, 208 ... Down counter, 240 ... Carry pulse generation unit, 248 ... Up counter, 250 ... Logic comparison unit, 252 ... Comparator

Claims (18)

A pulse signal regeneration device for removing noise contained in an input pulse signal,
A flip-flop having a set input terminal to which a set signal for setting an output is input and a reset input terminal to which a reset signal for resetting the output is input;
A noise monitoring unit that monitors noise included in the input pulse signal, and
The set signal is supplied to the set input terminal when the input pulse signal is asserted to set the flip-flop, and then the noise is removed in the noise monitoring unit without the noise. The pulse signal regeneration device, wherein the reset signal is supplied to the reset input terminal to reset the flip-flop when a removal target period has elapsed. The pulse signal reproducing apparatus according to claim 1, wherein the noise monitoring unit starts monitoring the presence or absence of the noise after the input pulse signal is negated. The pulse signal regeneration device according to claim 2, wherein the noise monitoring unit sets the noise removal target period when the input pulse signal is asserted. The pulse signal reproduction device according to claim 1, wherein the noise monitoring unit is configured to be able to arbitrarily set the noise removal target period. The pulse signal reproduction device according to claim 4, wherein the noise monitoring unit includes a setting circuit that sets the noise removal target period. The pulse signal reproduction device according to claim 4, wherein the noise monitoring unit sets the noise removal target period by software processing. The pulse signal regeneration device according to any one of claims 1 to 6, wherein the noise monitoring unit includes a counter that measures progress of the noise removal target period. The counter has a data input terminal to which noise gate data for defining the noise removal target period is set,
The pulse signal reproduction device according to claim 7, wherein the noise monitoring unit takes in the noise gate data into a data input terminal of the counter when the input pulse signal is asserted. The counter is a down counter and activates a borrow output when the noise removal target period has elapsed without the presence of the noise, and supplies the borrow output as the reset signal to the reset input terminal. The pulse signal regeneration device according to claim 8, wherein the flip-flop is reset. The counter is an up counter, and activates a carry output when the noise removal target period has elapsed without the presence of the noise, and supplies the carry output to the reset input terminal as the reset signal. The pulse signal regeneration device according to claim 8, wherein the flip-flop is reset. The counter is configured to stop the count operation while the reset signal is supplied to the flip-flop when an initial state and the noise removal target period have elapsed,
The flip-flop is set by receiving the set signal based on the assertion of the input pulse signal at the set input terminal in a state where the counting operation of the counter is stopped. The pulse signal reproducing device described in 1. The pulse signal regeneration device according to any one of claims 9 to 11, wherein the flip-flop is a set priority type flip-flop. The counter resets the flip-flop by supplying the reset signal to the reset input terminal when the noise removal target period has elapsed without the presence of the noise, and the initial state and the noise. It is configured to stop the count operation in a state where the reset signal is not supplied to the reset input terminal after the removal target period has elapsed.
The flip-flop is set by receiving the set signal based on the assertion of the input pulse signal at the set input terminal in a state where the counting operation of the counter is stopped. Pulse signal regeneration device. The counter supplies the reset signal to the reset input terminal of the flip-flop having no priority when the noise removal target period has passed without the presence of the noise, so that the flip-flop Configured to reset,
The noise monitoring unit is configured to capture the noise gate data into the data input terminal of the counter when the input pulse signal is at an assert level and when the flip-flop is in the reset state. The pulse signal reproducing device according to claim 8. The pulse signal reproducing device according to claim 13 or 14, wherein the counter is a down counter, and starts a counting operation from the set noise gate data during the noise removal target period. The noise monitoring unit sets noise gate data for defining the noise removal target period, compares the count value of the counter with the set noise gate data, and the noise does not exist A logic comparison unit that determines that the count value of the counter coincides with the noise gate data when the noise removal target period has elapsed and supplies the reset signal to the reset input terminal of the flip-flop;
The counter sets a count value to an initial state when the input pulse signal is at an assert level and when the flip-flop is in the reset state, the input pulse signal is at a negate level, and the flip-flop The pulse signal reproducing device according to claim 7, wherein a count operation is performed when is in the set state. The pulse signal regeneration device according to claim 16, wherein the counter is an up counter, and starts a count operation from zero which is the initial state in the noise removal target period. The pulse signal reproducing device according to claim 13, wherein the flip-flop is a flip-flop having no priority.

Images