JPH1070444A - Digital noise filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily remove a wide noise by starting/stopping the operation of a counting means by inputting a partial output, digital signal and clock signal by providing the counting means and an output judging means with which the output signal of that counting means is inputted and the output is sent when a count value reaches a fixed value. SOLUTION: When the noise is inputted, the output signal of an inverter 71 is changed to be high, and a count part 73 performs down counting. When an input signal Vi is changed to be high, the count part 73 performs up counting. When count values Q0-Q2 become 7 (1, 1, 1), the output of a 1st AND gate 80 turns high, and the output of a Q flip-flop 81 is set. Next, the output signal of the 1st AND gate 80 is inputted to a 2nd AND gate 75 and the output of the 2nd AND gate 75 turns high. As a result, the output of a 4th AND gate 78 turns high and corresponding to the noise input, up counting is performed once or down counting is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital noise filter, and more particularly, to measuring a position of a motor for controlling a position of a chip mounter provided for the purpose of transferring arbitrary characteristic parts in a factory automation system. The present invention relates to a digital noise filter suitable for removing noise input to an encoder circuit used.

In a robot controller, a die bonder, or the like, a motor is used to control the position, and the position of the motor is measured by an encoder. The encoder detects a position by receiving a signal generated from the motor, but it is difficult to accurately detect the position because noise is mixed in the signal. That is, in a chip mounter or a robot position controller using an encoder, noise generated from a driving motor flows into an encoder line, causing a deviation in the count value and a position error. Most of such noise is not removed by the analog filter, and it is difficult to block generation of the noise. Therefore, a digital noise removing circuit is required.

[0003] Conventionally, noise generated from the motor has been removed by using a low-pass filter or a shift register.

[0004]

2. Description of the Related Art A conventional technique will be described below with reference to the accompanying drawings. FIG. 1 is a configuration diagram of a conventional low-pass filter, FIG. 2 is a waveform diagram showing a concept of removing noise generated from a motor using the conventional low-pass filter, and FIG. FIG. 4 is a waveform diagram showing the concept of removing noise generated from a motor using a conventional digital noise filter using a shift resist. As shown in FIG. 1, the low-pass filter has the configuration shown in FIG.
An input signal as shown in FIG. 2A is input, and a signal as shown in FIG. 2B is output.

When a digital buffer is connected to the output signal and output, a waveform as shown in FIG. 2C is obtained.

However, conventionally, if a combination of a resistor R and a capacitor C is used to remove noise mixed in an encoder line, an input signal cannot be reproduced when the time constant is large, so that the time constant value is limited. There is a problem that there is. In practice, it usually does not have a sufficient time constant to eliminate noise entering the encoder line. Further, even if an attempt is made to precisely perform band separation using an inductor-capacitor combination or an active filter, it is difficult to precisely control the band when producing the filter because the filter is expensive to manufacture.

As another method, a configuration of a digital noise filter using a commonly used shift register is shown in FIG. As shown in FIG. 3, a conventional digital noise filter using a shift register requires one JK flip-flop in order to remove noise having a length corresponding to one cycle of a sampling clock signal. Also, as shown in FIG. 4, one or two widths of noise are removed by three D-type flip flops as a shift resist.

The details will be described below. As shown in FIG. 4, when the input signal Vi is input, a low signal is input first, so that the output of the D-type flip-flop 1 and the output signal of the JK flip-flop 6 become low signals. .

When the next clock signal CLK is input,
Although the force of the D-type flip-flop 1 becomes a high signal with the input signal, the output signal V of the JK flip-flop 6
O becomes a low signal through the AND gate 4 because the outputs of the other two D-type flip-flops 2 and 3 are low.

Since the input remains high even in the next clock signal, the output signals of the D-type flip-flops 1 and 2 become high, but the output signal of the D-type flip-flop 3 is low. As a result, the output signal VO becomes low.

When the next clock signal is input, the output signals of all the D-type flip-flops 1, 2, and 3 become high, and as a result, the high signal is output through the AND gate 4 to JK.
The input to flip-flop 6 results in output signal V
O goes high. This is shown in FIG.

When the next clock signal is input, since the input signal is high, the output signals of all the D-type flip-flops 1, 2, and 3 go high, and as a result, the high signal passes through the AND gate 4. Is input to the JK flip-flop 6, and as a result, the output signal VO goes high. This is shown in FIG.

When the next clock signal is inputted, at this time, one-width noise is inputted and the output of the D-type flip-flop 1 becomes low, but the outputs of the other D-type flip-flops 2 and 3 become low. Goes high. Then, the output of the AND gate goes low, the output of the NOR gate 5 goes low, and the output signal VO of the JK flip-flop 6 remains high without any change. This is shown in FIG.

As described above, noise of one width is removed, and noise of two widths is also removed. However, noise having a width as small as three clock signals is not removed. That is, in the prior art, four D-type flip-flops are required for that purpose.

As described above, a conventional digital noise filter using a shift resist requires a large number of flip-flops in order to remove long-width noise. That is, since a low frequency band signal has a long noise width, a large number of flip-flops are required to remove the noise. A digital noise filter using a conventional shift register has a problem that it is expensive.

[0016]

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital noise filter which can easily remove long-width noise and can be manufactured at low cost.

[0017]

According to the digital noise filter of the present invention, a digital signal is inputted, a counting means for counting up or down, an output signal of the counting means is inputted, and the count value is fixed. Output judging means for sending an output when the value reaches a value, and a state transition for starting or interrupting the counting operation of the counting means by receiving a digital output signal and a clock signal when a partial output in the output judging means is input And control means.

According to another aspect of the present invention, there is provided a motor, an encoder circuit for measuring the position of the motor, and a counting means connected to the motor and the encoder circuit for inputting a digital signal and counting up or down. An output signal of the counting means is input, an output determining means for outputting an output when the count value reaches a certain value, and a partial output in the output determining means is input, and the digital input signal and the clock signal are And a state transition control means for starting or interrupting the counting operation of the counting means upon input.

The technical principle used to carry out the present invention configured as described above is as follows. The digital level output from the encoder is counted by the sampling clock, and the encoder level output is determined from the count value. The counting of digital levels is based on a state transition diagram as shown in FIG. As shown in FIG. 5, the state moves between the 0 state and the N state depending on whether the state input to the state transition diagram in the initial arbitrary state is low or high. The output sets high in the N state, low in the 0 state, and the other state (1
-N-1), the previous output is maintained. As a result, in order for the output to be set (high) in the 0 state, the encoder output should be made high during N cycles, and a temporary low occurs due to noise in the middle of the encoder output being high. However, the output state does not change. Similarly, in order for the output to be reset (low) in the N state, the encoder output is low for N cycles, and the output state does not change even if a temporary high occurs in this process. This is shown in FIG.

The encoder noise band to be removed by this technical principle can be set by adjusting the sampling clock and the maximum count value of the counter. In other words, noise can be removed with NB (number of bits) flip-flops that satisfy Expression 2 ^NB > the noise width to be removed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments in which the present invention can be implemented will be described below with reference to the accompanying drawings.

FIG. 7 is a block diagram of a digital noise filter according to an embodiment of the present invention. As shown in FIG.
The configuration of the digital noise filter according to the embodiment of the present invention includes a counting unit 73 for receiving an input signal passing through the inverter 71 and performing up or down counting. Further, a first NOR gate 79 connected to the three output signals of the counting section 73, a first AND gate 80 connected to the three output signals of the counting section 73,
A reset terminal is connected to the gate 79, and a Q flip-flop 81 whose set terminal is connected to the first AND gate 80. An output determination unit 74 for outputting when the count value reaches a certain value is provided. . The input signal Vi is input to the inverting terminal via the inverter 71, and the first A
A second AND gate 75 is provided to receive the output of the ND gate 80, and a third AND gate 76 is provided to receive the signal inverted by the inverter 71 and the output signal of the first NOR gate 79. These second AND
The output signals of the gate 75 and the third AND gate 76 are
The logical value is input to the NOR gate 77 and subjected to logical operation, and the calculated value is output to the clock signal terminal of the counter 73. That is, the output of the second NOR gate 77 is
The clock signal CLK is input to one input of the D-gate 78 and the other input of the fourth AND gate 78. Then, the output of the fourth AND gate 78 is
3 clock signal terminal. A second AND gate 75, a third AND gate 76, a second NOR gate 77
And the fourth AND gate 78 as a whole
A state transition controller 72 for starting or interrupting the counting operation is formed.

The operation of the digital noise filter according to the embodiment of the present invention having the above configuration is as follows. First, when power is applied by the user, the operation of the digital noise filter according to the embodiment of the present invention starts. When the operation starts, the input signal Vi having the waveform shown in FIG. 6 is input to the inverter 71, and the clock signal CLK is changed to the fourth AND signal.
Input to gate 78. First, when a high signal is generated, a low signal is input to the counting unit 73 through the inverter 71, and the counting unit 73 counts up. Next, when a clock signal is input, the counting unit 73 outputs the input signal Vi.
Is high, so upcounting follows.

When the noise corresponding to the three-width clock signal is input in this manner, the output signal of the inverter 71 changes to high, and the counter 73 counts down during the three clock signal periods. . FIG. 6 shows the waveform at this time. Next, when the input signal Vi changes to high again, the counting unit 73 performs up-counting again. Thus, the count values Q0, Q1, Q2 are 7 (1, 1,
At 1), the output of the first AND gate 80 goes high and the output of the Q flip-flop 81 is set.
Next, the output signal of the first AND gate 80 is input to the second AND gate 75, and the output of the second AND gate 75 becomes high.

Then, the output of the second NOR gate 77 goes low, and as a result, the output of the fourth AND gate 78 goes low, and the counting section 73 does not count.
When the input signal Vi changes to low, the second AND gate 75
Goes low, and the output of the second NOR gate 77 goes high. Then, when the output of the fourth AND gate 78 goes high and the counting section 73 performs down-counting and receives a noise corresponding to a single-width clock signal, the counting section 73 performs up-counting once and down-counting. Then, the count values Q1, Q2, and Q3 are 0 (1,
At 1, 1), the output of Q flip-flop 81 goes low. The waveform at this time is shown in FIG.

By the above operation process, a waveform for removing noise as shown in FIG. 6 can be obtained. In the above process, the counting unit was constituted by four flip-flops so as to remove noise corresponding to a clock signal having a width of seven. However, a digital noise filter using a conventional shift register requires eight flip-flops. Also, in the above process, a counting unit for removing noise having a length corresponding to a clock signal having a width of seven was used.
Easy to expand in any way.

[0027]

As described above, according to the embodiment of the present invention, it is possible to provide a digital noise filter which has an advantage that it can easily remove noise having a long width and can be manufactured at a low cost.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a conventional low-pass filtration filter.

FIG. 2 is a waveform diagram illustrating a concept of removing noise generated from a motor using a conventional low-pass filter.

FIG. 3 is a configuration diagram of a digital noise filter using a conventional shift register.

FIG. 4 is a waveform diagram illustrating a concept of removing noise generated from a motor using a conventional digital noise filter using a shift register.

FIG. 5 is a state transition diagram of a basic principle of a digital noise filter according to an embodiment of the present invention.

FIG. 6 is a waveform diagram of each signal of a digital noise filter according to an embodiment of the present invention.

FIG. 7 is a configuration diagram of a digital noise filter according to an embodiment of the present invention.

[Explanation of symbols]

 71 inverter 72 state transition controller 73 counting unit 74 output judging unit 75 second AND gate 76 third AND gate 77 second NOR gate 78 fourth AND gate 79 first NOR gate 80 first AND gate 81Q flip-flop

Claims (9)

[Claims] 1. Counting means for receiving a digital signal and counting up or down; and output determining means for receiving an output signal of the counting means and transmitting an output when a count value reaches a certain value. A digital input signal receiving part of the output judging means, a digital input signal and a clock signal being inputted, and a state transition control means for starting or interrupting a counting operation of the counting means. noise filter. 2. The counting means is capable of counting up or down as a counting unit, and removes noise having a length corresponding to a clock signal having seven widths by using three outputs. Item 7. A digital noise filter according to Item 1. 3. The output determining means includes: a first NOR gate 79 connected to three output signals of the counting means; a first AND gate 80 connected to three output signals of the counting means; 2. The digital noise filter according to claim 1, further comprising a Q flip-flop 81 having a reset terminal connected to the gate 79 and a set terminal connected to the first AND gate 80. 4. The state transition control means according to claim 2, wherein an input signal Vi passing through an inverter 71 is inputted at an inverting terminal, and an output of said first AND gate 80 is inputted at a second terminal.
A third signal whose output signal is input to the AND gate 75, the signal inverted from the inverter 71, and the first NOR gate 79
AND gate 76, the second AND gate 75 and the third
A second output signal to which the output signal of the AND gate 76 is inputted and which performs a logical operation on the clock signal terminal of the counter 73
2. The digital noise filter according to claim 1, comprising: a NOR gate 77; and a fourth AND gate 78 to which an output of the second NOR gate 77 is input and a clock signal CLK is input to the other side. 5. Counting up or down to output a counting value proportional to a digital input signal external to the counter; generating an output signal when the counting value reaches a constant value; Generating a feedback signal corresponding to the following: generating a counter input signal from an external digital input signal, an external clock signal, and a feedback signal; and controlling a counting value using the counter input signal. A method for effectively removing long-length noise. 6. The method according to claim 5, wherein the counting step comprises a counting up or down auxiliary step for controlling noise corresponding to the length of the additional seven clocks. 7. A motor; an encoder circuit for measuring the position of the motor; counting means coupled to the motor and the encoder circuit for receiving a digital signal and counting up or down; and an output of the counting means. An output determining means for transmitting an output when a signal is input and the count value reaches a certain value; a partial output in the output determining means is input, a digital input signal and a clock signal are input, and the counting means A system including a digital noise filter, comprising: a state transition control unit for starting or interrupting a counting operation. 8. The system according to claim 7, wherein the counting means counts up or down to control noise corresponding to seven clock periods of the external clock signal. 9. The output control means includes: a first NOR gate 79 connected to three output signals of the counting means; a first AND gate 80 connected to three output signals of the counting means; The system of claim 7, comprising a Q flip-flop 81 having a reset terminal connected to the gate 79 and a set terminal connected to the first AND gate 80.