DE19712790A1 - Digital noise filter for position control of robot used in die bonding - Google Patents

Abstract

The filter includes a two-way counter (73), an output control circuit (74), and a state change control circuit (72). The counter responds to an external digital input signal (Vi) and generates a count value. The output control circuit generates an output signal when the counter value has reached a preset value, while it also generates a feedback signal. The state change control circuit uses the external, digital input signal, an external clock pulse signal, and the feedback signal to regulate the counter. The counter preferably counts up or down to filter-out noise, corresponding to a length of seven clock cycles of the external clock pulse signal. Typically the output control comprises a first NOR-gate (75) and a first AND-gate (80), and a Q flip-flop (81).

Description

The present invention relates to digital noise filter for filtering one supplied to a coding circuit prolonged input noise, the coding circuit the position of an engine. The motor controls or regulates the position of a chip-mounting device, which special components in a factory automation system transported.

In general, a motor controls the position a chip mounting device of a robot controller or one Matrix connector or so-called "die bonder". A knockout The device determines the position of the motor accordingly chend a signal generated by the engine. However, the Po sition of the motor is not with appropriate accuracy be measured since the motor generates noise in the signal. The value of the input signal is incorrect because it is from Drive motor generated noise of the encoder leads, so that position error of the chip assembly device or the control device for the robot posi tion result.

Noise cannot be used with an analog filter effectively exclude so that the generation of errors cannot be easily prevented. For this green digital noise elimination circuits must be turned on be set. The state of the art usually Low pass filter or shift register in such a scarf used to switch off the noise.

Fig. 7 shows a known low-pass filter. 11 Fig. 2A shows a signal with noise or noise, which is the known th low-pass filter 11 of Fig. 7 is supplied. Fig. 2B shows the signal output from the low-pass filter. 11 Fig. 2C shows the situation when the output signal of the Tiefpaßfil 11 a digital buffer 12 is supplied ters, said digital buffer 12 eliminates noise and outputting a noise-free signal.

When using a low-pass filter 11 to filter out noise, however, the input signal cannot be restored or regenerated if the time constant is long or long. The noise suppression efficiency of the low-pass filter 11 is thus limited by the time constant of the filter. In fact, the low-pass filters do not have sufficiently small time constants to remove the noise supplied to the encoder line.

Combinations of inductor and capacitor or active fil ter can be used to separate the frequency bands nen. However, such circuits are only expensive producible and can not be enough with the tape separation Control or regulate the appropriate accuracy.

Fig. 3 shows a digital noise filter or noise filter with a shift register for removing noise. The digital noise filter uses a shift register with a JK flip-flop to remove noise corresponding to a period (cycle) of the sampling clock signal and with three D flip-flops to reduce the noise according to the length of one or two clock signals to be effectively eliminated.

Fig. 4 shows the D-type flip-flop 1 supplied to input signal Vi. Initially, the input signal Vi is at a low level, as a result of which the output signal of the D flip-flop 1 is at a low level. As a result, the output signal level Vo of the JK flip-flop 6 also has a low level.

When the D flip-flop 1 receives the input clock signal CLK, the output signal from the D flip-flop 1 becomes high due to the high level of the input signal Vi.

Since the output signals of the D flip-flops 2 and 3 still have a low level, the output signal of the AND gate 4 also has a low level. Accordingly, the output signal Vo of the JK flip-flop 6 remains at a low level.

During the next clock cycle of the input clock signal CLK, the output signals of the D flip-flops 1 and 2 change their level to a high level because the input signal Vi is at a high level. Since the output signal of the AND gate 4 remains at a low level, the output signal Vo of the JK flip-flop 6 also remains at the low level.

During the following clock cycle of the input clock signal CLK, the output signals of all D flip-flops 1 , 2 and 3 have high levels, since the level of the input signal Vi remains high. Accordingly, the output signal of the AND gate 4 takes a high level, whereby the level of the output signal Vo of the JK flip-flop 6 becomes high.

During the next clock cycle of the input clock signal CLK, the output signal of the D-flip-flop 1 changes its level to a low level, since the input signal Vi has a noise component which devalues the signal level to low (noise ( 1 )). However, the output signals of the D flip-flops 2 and 3 maintain their high level. As a result, the output signal of the AND gate 4 and the output signal of the NOR gate 5 is at a low level and the output signal Vo of the JK flip-flop 6 is at a high level ( FIG. 4).

As a result, the digital noise filter eliminates noise which lasts for one or two cycles of the clock signal CLK. However, the digital noise filter can operate over three clock cycles do not effectively switch off continuous noise. To do that eliminating noise over three clock cycles, would the digital noise circuit or noise circuit an additional D flip-flop or a total of four D flip-flops need.  

Thus, known digital noise filters with a slide are required register multiple flip-flops to last for several To hide clock signals continuous noise signals. The white teren is the production of the well-known digital noise film filtering out noise is very cost-intensive because the Low frequency band signal noise generally lasts for a relatively long period of time.

It is an object of the present invention, a system and to create a process that is long in simple form continuous noise persisting over several clock cycles switched off.

According to the invention, the task is achieved by the combination of features tion of claim 1, 5 or 7 solved; the subclaims have preferred embodiments of the invention for Content.

According to the invention, an effective mechanism is created fen, which addresses the above problems of the known Avoids switching and continues over several clock cycles continuous, long-lasting noise eliminated.

According to a preferred embodiment of the above invention is a digital noise filter created which eliminates long-lasting noise. The digital one Noise filter has a counter, an output control or regulating device and a control or regulation device for the change of state.

The digital noise filter counts the digital level of one external digital signal, which from a coding scarf device was output by sampling the clock signal, and determines the starting level according to the count of the Coding circuit.

The counting device counts according to the external digital  signal up or down. The output control rule direction emits an output signal when the count value of the Counting device reaches and generates a predetermined value a feedback signal. The control device for the change of state begins or interrupts the loading powered the counter using an input signals of the counter, which is from the external digital signal, an external clock signal and the feedback signal nal generated by the output control device has been. If the output of the control device for the Change of state either the status "SET" (high level) or reached the status "RESET" (low level), the output remains immune to noise which external digital signal for a period of clock cycle len occurs.

The length of noise to be removed can be determined by controlling the sampling clock signal and the count value of the counting device. Especially when 2 ^NB <noise length, the noise can be effectively eliminated by using only one NB number of flip-flops.

Other tasks, characteristics and basic principles of the present ing invention are based on an embodiment explained in connection with the accompanying drawing. It shows:

FIG. 1 is a digital noise filter according to the invention;

Figs. 2A to 2C are timing charts of the signal flow in the known low-pass filter;

Figure 3 shows a known digital noise filter with sliding register.

Fig. 4 is a timing chart of the signal flow in the known di gital noise filter;

Fig. 5 is a state diagram of the operation of the present invention;

Fig. 6 is a timing chart of the signal flow of an inventive digital noise filter; and

Fig. 7 shows a known low-pass filter.

The following detailed description of the invention in Ver binding with the accompanying drawing explains preferred Embodiments of the basic principles of the invention. On Embodiments are possible without the protective cover begin to leave the invention. The following detailed Description does not limit the invention. Instead the scope of the invention is illustrated by the attached Claims and their equivalents defined.

Fig. 1 shows a digital noise filter in accordance with the principles of the present invention. The digital noise filter has a counting device 73 , an output control or regulating device 74 - is called output control device in the following - and a control or regulating device 72 for the change of state - is called control device in the following -.

The counter 73 receives an inverted external digital input signal Vi from the inverter 71 . The counting device 73 counts up or down according to the inverted input signal Vi.

The output controller 74 outputs a signal when the count of the counter 73 reaches a predetermined value. The output control device 74 has a first NOR gate 79 and a first AND gate 80 , both of which are connected to three output terminals Q0, Q1 and Q2 of the counter device 73 . The output controller 74 also includes a Q flip-flop 81 with a reset terminal which is connected to the first NOR gate 79 and a set terminal which is connected to the first AND gate 80 .

The state change control device 72 controls the count by the counter 73 using the external digital input signal Vi, a clock signal CLK and a feedback signal of the output control device 74 . The control device 72 has a second AND gate 75 , which receives the inverted input signal Vi from the inverter 71 with its inverted connection and the output of the first AND gate 80 with its non-inverted connection. The control device 72 also has a third AND gate 76 , which receives the inverted input signal Vi from the inverter 71 and the output from the first NOR gate 79 with their non-inverted connections. The outputs of the second AND gate 75 and the third AND gate 76 are supplied to the second NOR gate 77 . The output of the second NOR gate 77 is supplied to the fourth AND gate 78 together with the clock signal CLK. The output of the fourth AND gate 78 forms an operating value to be supplied to the clock signal connection of the counter 73 .

FIG. 5 summarizes the state diagram representation of the operation of the control device 72 for the state change. The status of the control device 72 for the state change changes from the "zero" state to the "N" state in accordance with the state of the external digital input signal Vi. The output of the state change controller 72 reaches the "RESET" state when the state is "0" (low) and the "SET" state when the state is "N" (high). The output of the control device 72 for the state change remains in the previous state, in the states "1 to N-1". Thus, the output of the encoder must be high when the output of the Steuereinrich device 72 is "SET" from the "0" state. Accordingly, the output of the encoder must be low when the output of controller 72 is set to the "N""RESET" state. As a result, the output of the state change controller 72 is not affected and maintains its previous state even if the noise present in the external digital input signal Vi inverts the signal for a period of time.

As soon as energy is supplied, the digital noise filter begins to work. At this time, as shown in FIG. 6, the external digital input signal Vi is supplied to the inverter 71 and the clock signal CLK is supplied to the fourth AND gate 78 .

Fig. 6 shows that the output of the inverter 71 is set to a low level as soon as the external digital input signal Vi assumes a high level. Since the output of the inverter 71 is supplied to the counter 73, the counter 73 starts counting upwards. The counter 73 continuously increases its value based on the clock signal CLK, since the external digital input signal Vi is at a high level.

If noise interferes with the external digital input signal Vi, so that its level is changed to a low level, which is maintained for a period of three clock cycles (noise ( 3 )), the output of the inverter 71 is changed to a high level and the Counter 73 counts down during the three clock cycles.

When the level of the external digital input signal Vi is changed to a high level, the counter 73 starts counting up again. When the counter 73 reaches "7" so that Q0 = 1, Q1 = 1 and Q2 = 1, the output of the first AND gate 80 is changed to a high level and the output of the Q flip-flop 81 is set, thereby the output signal Vo migrates to a high level ( FIG. 6). Since the output of the first AND gate 80 is supplied to the second AND gate 75 , the output of the second AND gate 75 changes to a high level. Accordingly, the output of the second NOR gate 77 changes to a low level, whereby the output of the fourth AND gate 78 moves to a low level. Thus, the counter 73 ends the counting up.

When the external digital input signal Vi is changed to a low level, the output signal of the second AND gate 75 also moves to a low level, so that the output of the second NOR gate 77 takes a high level. As a result, the output of the fourth AND gate 78 is set high, triggering the counter 73 to start counting down.

When noise affects the external digital input signal Vi, so that its level is set to a high level which continues for a period of one clock cycle (noise ( 1 )), the counter 73 starts counting up. When the external digital input signal Vi is changed to a low level, the counter 73 starts counting down again. When the counter 73 reaches "0" so that Q0 = 0, Q1 = 1 and Q2 = 0, the output of the first NOR gate 79 is changed to a high level so that the Q flip-flop 81st is reset. As a result, the output signal Vo of the Q flip-flop 81 is changed to a low level.

The output signal Vo represents the resulting signal wel lenform, which ent through the digital noise filter generated the basics of the present invention becomes. The present invention only sets four flip-flops to noise with a length of seven clock cycles to eliminate while the well-known digital noise filter  eight flip-flops are required to achieve the same amount of noise dazzle. Accordingly, the present invention provides one improved and more effective digital noise filter, which noise is inexpensive and with corresponding accuracy eliminated.

In summary, the present invention relates to a digital filter for eliminating input noise from a coding circuit. The digital filter has a counter circuit 73 , an output control circuit 74 and a control circuit 72 for the change of state. The counter circuit counts up or down in accordance with an external digital input signal Vi. The output control circuit 74 generates a signal when the count value of the counter circuit 73 reaches a predetermined value and also generates a feedback signal. The control circuit 72 starts for the change of state or interrupts the operation of the counting circuit 73 by an input signal of the counter is supplied to the 73rd The control circuit 72 for the state change he witnesses the input signal of the counting device from the exter NEN digital input signal Vi, an external clock signal and the feedback signal from the output control circuit 74th

The foregoing description of preferred embodiments games of the present invention is for Dar only position and explanation, but not for limitation the specifically presented form of the invention. Further executions tion examples of the invention are taking into account the Description and practical implementations of the invention conceivable. The description and exemplary embodiments serve for explanation only, the scope of protection of the inven by the appended claims and their equivalents is set.

Claims (9)

1. Digital noise filter to effectively eliminate long-term noise, with:
counting means ( 73 ) for counting up and down in accordance with an external digital input signal (Vi) and for generating a count value;
output control means ( 74 ) for generating an output signal when the count value reaches a predetermined value and for generating a feedback signal; and
a control device ( 72 ) for the change of state, which controls the counting device ( 73 ) by means of an input signal for the counting device, the control device ( 72 ) for the change of state the counting device input signal from the external digital input signal (Vi), an external clock signal and the feedback signal is generated. 2. Digital noise filter according to claim 1, characterized in that the counting device ( 73 ) counts up or down to filter out noise corresponding to a length of seven clock cycles of the external clock signal. 3. Digital noise filter according to claim 1 or 2, characterized in that the output control device ( 74 ) comprises:

• - An output controller for outputting the output signal when the count value reaches the predetermined value, the output controller having a first NOR gate ( 79 ) and a first AND gate ( 80 ), both of which have three output terminals (Q0, Q1 , Q2) the counting device are connected, and
• - A Q flip-flop ( 81 ) which has a reset connection connected to the first NOR gate ( 79 ) and a connection connected to the first AND gate ( 80 ).

4. Digital noise filter according to claim 3, characterized in that the control device ( 72 ) for the state change comprises:
a second AND gate ( 75 ) for receiving the external digital input signal (Vi) and an output signal of the first AND gate ( 80 );
a third AND gate ( 76 ) for receiving the external digital input signal (Vi) and an output signal of the first NOR gate ( 79 );
a second NOR gate ( 77 ) for receiving output signals from the second AND gate ( 75 ) and the third AND gate ( 76 ); and
a fourth AND gate ( 78 ) for receiving an output signal from the second NOR gate ( 77 ) and an external clock signal, and for outputting the counter input signal. 5. A method of effectively eliminating long-term noise, comprising the steps of:
Counting up or down to generate a count according to an external digital input signal (Vi) of a counting device;
Generating an output signal when the count value reaches a predetermined value;
Generating a feedback signal corresponding to the count value;
Generating a counter input signal from the external digital input signal (Vi), an external clock signal and the feedback signal; and
Control of the count value by the counter input signal. 6. The method according to claim 5, characterized in that the counting step is a sub-step to start up or run has to count to a corresponding to a length of seven clock cycles to eliminate sustained noise. 7. system, with:
an engine;
a coding circuit which determines a position of the motor; and
a digital noise filter, which is connected to the motor and the coding circuit, the filter comprising:
a counter ( 73 ) which counts up or down to generate a count according to an external digital input signal (Vi);
output control means ( 74 ) for generating an output signal when the count value reaches a predetermined value and for generating a feedback signal; and
a control device ( 72 ) for the change of state which controls the counter by a counter input signal, the control device ( 72 ) for the change of state generating the counter input signal from the external digital input signal (Vi), an external clock signal and the feedback signal. 8. System according to claim 7, characterized in that the counting device ( 73 ) counts up or down to filter out noise corresponding to a length of seven clock cycles of the ex-internal clock signal. 9. System according to claim 7 or 8, characterized in that the output control device ( 74 ) an output control for outputting the output signal when the count value reaches the predetermined value, the output control from a first NOR gate ( 79 ) and one has a first AND gate ( 80 ), both of which are connected to three output terminals (Q0, Q1, Q2) of the counting device, and a Q flip-flop ( 81 ) which has one with the first NOR gate ( 79 ) connected reset connection and having a connection terminal connected to the first AND gate ( 80 ).