JPS5875319A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To ensure the smooth separation and decision with high accuracy and high stability for a signal processing circuit which performs the separation and decision between noise and a signal, by comparing a high or low signal level with the width of the desired set time. CONSTITUTION:A pulse conversion is carried out for an input signal on the basis of a specified threshold level, and this converted pulse is fed to an up- down counter 13 to be compared with the preset value. Thus the signal is decided as a high or low level when the pulse is larger than the preset value and then delivered. As a result, the separation is possible between noise and a signal regardless of the frequency or the signal level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing circuit that performs separation judgment between a signal and noise.

In recent years, many systems have been developed in which a device or device itself receives analog or digital signals from an external sensor or other device, processes these signals in a predetermined manner, and performs appropriate operations. Incidentally, these external signals are easily affected by disturbance noise, and it is essential for the stable operation of the equipment to remove the noise and extract the desired signal. In particular, when sensors or external equipment are located far apart and the impedance of their signal lines is high, they are susceptible to noise, and when the confidence level is low, it is difficult to separate the desired signal from noise. .

Conventionally, in order to remove noise applied to such a signal line, as shown in FIG. By lowering the gain of unnecessary frequency components included in the signal, noise is separated from the desired signal. However, with this method of separating signals and noise based on their frequency characteristics, when the frequency component of the noise filter is low, the separation becomes more difficult, especially as the signal becomes a lower level signal, causing phenomena such as signal delay. However, there was a drawback that the signal waveform was deformed.

The present invention has been made to solve the above-mentioned drawbacks.
Rather than separating the signal and noise based on frequency characteristics, the time width of the signal's low level or low level is compared with a predetermined set time, and when the time width is greater than or equal to the set time, the signal is set to high level. Another object of the present invention is to provide a signal processing circuit that can smoothly, accurately, and stably separate noise and signals regardless of frequency or signal level by having a circuit configuration that determines that the signal is low level and outputs it. OBJECTIVES Hereinafter, one embodiment of the present invention will be explained with reference to the drawings. In the signal processing circuit shown in FIG.
Voltage comparator for converting to 2 or 10m digital signal, 12 is AND circuit ANDJ and ANDj and inverter! , and @ from the voltage comparator 11
1m, a decoding circuit that decodes the reference clock as an up signal or a down signal according to the digital signal of @Q#, and 13 is a decoding circuit that decodes the reference clock as an up signal or a down signal from the decoder circuit 12.
Up/down counter with bit preset function,
This counter IJ carries each carry C when the count is over.
A or Pollo Bo signal is output. A negative logic OR circuit 14 receives the carry Ca or borrow Bo signal from the counter 13 and generates load signals 1 and 0, thereby loading the preset input into the counter 13.
5 is set by the carry signal C1 from the counter 13 and reset by the borrow signal Boζ.
-8 flip-flop circuits, and the flip-flop circuit 15 outputs a control signal for the operation of the converter.

According to the above signal processing circuit, the input signal is input to the voltage comparator 11.
is converted into a @1' or 10'' digital signal based on a specific 7 ratio level vth and guided to the decoding circuit 12, and the digital signal has a logic level of 1.
When the logic level is 1'', it becomes an up clock output, and when the logic level is 0, it becomes a down clock output, which is applied to the up/down counter JJf. This up/down counter 13
is N bits and its preset input is set to 2N/2, then this preset value is
It is set in the counter 13 by the load signal Lo from the negative logic OR circuit 14 at the signal timing of the carry Ca or borrow BO from 3. When the counter 13 continues to go up and down from the up-clock output or down-clock output ζ, the flip-flop circuit 15 is set by the carry signal Ca, and the flip-flop circuit 15 is reset by the borrow signal Bo. There is.

The operation will be explained in more detail with reference to the time chart in FIG. Now, assuming that the cylindrical part of the reference clock is T, when the input signal is C-level 1Lm in the initial state, it is lower than the threshold level vth as shown in Figure 3, so the voltage comparator 11 outputs @02 level. However, the decoder circuit 12 applies the reference clock as a down clock to the counter 13 through the AND circuit ANDJ. In response to this down clock, the counter 913 starts counting down, but the counter 13 always receives a pollo signal Q within 2° x i time.

Output. In response to this borrow signal Bo, the flip-flop circuit 15 is reset, so that the control signal becomes the @0 level state. At this time, the load signal 1.0 is output from the OR circuit 14 in response to the borrow signal BO, so the preset value 2N/2 is loaded into the counter 13.

Next, the high level @ for a set time until the counter 13 overflows, that is, less than 2N/2 x 7 hours
When an input signal of H# is applied, the output of the voltage comparator 11 becomes @1# level, and an up clock is sent from the AND circuit AND2 of the decoder circuit 12 to the counter 13. The 0 counter 13 starts counting up. However, up-counting is not continued until the carry signal Ca is output, and before that, the input signal becomes low level, and conversely, down-counting starts, and the flip-flop circuit 15 maintains the above-mentioned reset state. The control signal remains at 10" level J and then becomes high level @H" until it exceeds 2"/2X time".
When the input signal is applied, the counter 13 counts up every time the up clock is input, as described above, until the counter 13 overflows. Then, when the carry signal Ca is output, the flip-flop circuit 15 is switched to the set state. Therefore, the control signal becomes @1" level state. At the same time, the preset value is loaded at the timing of this carry signal Ca,
Let the content of the counter 13 be 2N/2. The input signal is high-repe. When holding @H1, counter 13
The carry signal (,a) is repeatedly sent out every time the period exceeds T, thereby holding the flip-flop circuit 15 in the set state.In other words, for an input signal with a pulse width exceeding the set time of 2''/2×T, It determines that it is a desired input signal and sets the control signal to logic level 11111.

Also, the input signal is from high level 1H' to low level 1L.
'', as described above, the flip-flop circuit 15 does not operate for the input signal of low level @L' that is less than 2''/2XT time, and the flip-flop circuit 15 does not operate for the input signal of low level @L1 that exceeds 2''/2XT time. The flip-flop circuit 15 operates only in response to the input signal and switches from the set state to the reset state.Furthermore, when the input signal continuously repeats high level @Hm and low level 1L'' within 2N/2XT time, ,)1 high level @H” and low level @L
Since the counter 13 repeats up-counting or down-counting in response to the time ``, the flip-flop circuit is activated when the absolute value of the time difference between the high-level time and the low-level time matches the set time 2N/2×d. 15 is determined.In other words, if the high level is 1Hm and the state coincides with the above set time 2°/2×T, the flip-flop circuit 15 is in the set state, and if the flip-flop circuit 15 is at the low level @L'', it is in the reset state. becomes. A majority vote is made to determine which polarity has the most time.

The above-described operation enables the signal processing circuit to separate a desired signal and noise from the input signal based on the time width of the predetermined set time 2'/2XT. The separation resolution can be arbitrarily designed by changing the bit length N of the up/down counter 13 and the frequency 1/T of the reference clock. Furthermore, by appropriately selecting the preset value of the counter 13, the positive and negative polarities of the input signal can be individually weighted and separated.

According to the above signal processing circuit, the input signal is converted into a pulse based on a certain threshold level vth, and judgment is made based on the pulse width of this converted pulse, so the filter function is independent of the signal level. can have.

In addition, since digital processing is used, if the minimum value of the positive or negative pulse width of the desired signal is known in advance, not only can the filter function be freely designed based on the pulse width ζ. , can perform reliable operations. Furthermore, even when there is noise such as the input signal repeating positive and negative polarities (such as relay bounce), the internal time majority judgment function sets the polarity to the one with the greater total of positive or negative times. This has the advantage of being able to perform stable operations.

Note that the present invention can also be applied to signal processing in which an input signal sent out with a positive or negative duty ratio is converted into a positive or negative logic signal in accordance with the duty ratio.

As explained above, according to the present invention, instead of separating signals and noise based on frequency characteristics, the time width between the high level or low level of the signal and a predetermined set time is compared, and when the time width is equal to or greater than the set time, Since the signal is determined to be high level or low level and output, a signal processing circuit that can perform smooth, accurate and stable separation of noise and signal regardless of frequency or signal level is used. Can be provided.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional processing circuit, FIG. 2 is a configuration diagram of a signal processing circuit according to an embodiment of the present invention, and FIG. 3 is a time chart for explaining the circuit operation of FIG. 2. . 10... Signal processing circuit, 11... Voltage comparator, 12
. . . decoder circuit, 13 . . . up/down counter, 14 . . . negative logic OR circuit, 15 . . . R-8 flip-flop circuit.

Claims (1)

[Scope of Claims] (1) Conversion means for converting an input signal into a @11 or @01 digital signal, and decoding a reference clock as an up-clock output or a down-clock output according to the digital signal from the conversion means. a decoding means for
an up/down counter with a preset function that counts up or down according to the up clock output or down clock output from the decoding means, and can arbitrarily vary the set time until overflow;
The counter includes a flip-flop circuit that is set and reset by a carry or borrow overflow output from the counter, and detects when the time width of the digital signal from the conversion means is longer than the set time, and controls the overflow of the counter. /(-70- output sets the flip-flop circuit to a specific state, and a desired 11", '0" signal from which noise is removed from the input signal is obtained from the flip-flop circuit. (2) When the digital signal from the conversion means continuously repeats the levels of @1m and @0'' within the set time, the total time width of the @12 level signal and the 10'' level signal (3) The signal processing circuit according to claim 1, further comprising means for setting the flip-flop circuit to a level having a larger time width among the total time widths. The signal processing according to claim 1, wherein the converting means is a voltage comparator that converts the input signal to a logic level signal of @1'' or @Om with respect to a predetermined threshold level. (4) The signal processing circuit according to claim 1, wherein the setting time of the counter can be arbitrarily set depending on the bit length of the counter and the frequency of the reference clock.