JPH06204867A - Automatic offset controlling circuit - Google Patents

Abstract

PURPOSE:To quickly converge the offset of a signal to '0' and to prevent a normal signal waveform including no offset from being deformed by offset control. CONSTITUTION:An U/D counter 36A counts up a difference between the negative frequency and positive frequency of a code SGN synchronously with a conversion completion signal EOC. When the count value exceeds 32, an overflow output terminal OVF is turned to '1' and voltage VR is impressed to an integrating circuit 31. When the count value becomes <=0, an underflow output terminal UNF is turned to '1', voltage -VR is impressed to the circuit 31, and before starting offset compensating operation, whether offset compensation is to be executed or not is carefully judged. Since the offset compensating operation is executed until the inversion of the code SGN is detected by an edge detecting circuit 372, offset can quickly be converged to '0'. At the time of detecting the inversion, a value PV=16 is loaded to the counter 36A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic offset adjusting circuit for use in a codec (encoder & decoder) of a telephone exchange subscriber circuit, an audio device, etc. and for removing a signal offset.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional offset automatic adjustment circuit of this type.

The A / D converter 10 uses the clock CLK as a conversion start signal and the analog signal AI as a digital signal D.
When it is converted to O and the digital signal DO is determined, the conversion end signal EOC is output. The digital signal DO includes the sign bit SGN. For example, the sign bit SGN is "1" (high level) when the value of the digital signal DO is positive, and "0" when the value of the digital signal AO is negative. '
(Low level).

A circuit 20 for converting the signal vi into the signal AI is connected to the preceding stage of the A / D converter 10. Circuit 2
0 is, for example, a bandpass filter, and is an operational amplifier 2
1 is provided. The time average value of the signal vi is 0 V, but the base of the input stage transistor pair of the operational amplifier 21 is
Due to the voltage imbalance between the emitters, the time average value of the signal AI deviates from 0V. The operational amplifier 21 usually has an offset null terminal to which an offset compensation circuit 22 is externally attached. When the signal AI when the offset compensation voltage C input to the offset compensation circuit 22 is constant at 0V is represented as AI0, AI = AI0−αC. Where α is a positive constant.

An automatic offset adjustment circuit 30 is provided to automatically adjust the offset of the signal AI to zero. The circuit 30 includes an integrating circuit 31 and a selector 32. The selector 32 selects and outputs the reference voltage VR when the code bit SGN is "0", and selects and outputs the reference voltage -VR when the code bit SGN is "1". The integration circuit 31 integrates the output of the selector 32 for a certain short time in synchronization with the conversion end signal EOC, and supplies the result as an offset compensation voltage C to the offset compensation circuit 22.

In the above configuration, for example, the signal vi is 0
When the signal AI0 is a positive constant voltage as shown in FIG. 9A at V, the sign bit SGN, the conversion end signal EOC, the offset compensation voltage C and the signal AI are respectively shown in FIG. 9B.
.. (E), the signal AI converges to 0V.

However, when the signal AI0 has a waveform as shown in FIG. 10A, the sign bit SGN and the conversion end signal E are used.
The OC, the offset compensation voltage C, and the signal AI change as shown in FIGS. 10B to 10E, and even if the signal AI0 does not include an offset, the offset adjustment works and the waveform of the signal AI is normal. The waveform of the signal AI0 is transformed. That is, the offset adjustment is too effective.

Therefore, an automatic offset adjusting circuit 30A as shown in FIG. 11 is used. This circuit 30A
Is an integrating circuit 31, a selector 32A, an inverter 33,
AND gates 34 and 35, up / down counter (U /
A D counter) 36 and an OR gate 37.

The U / D counter 36 is set to the value PV = 16 when the load control input terminal L is "1", for example.
When the count value becomes 32 or more, the overflow output terminal O
When the VF transitions to "1" and the count value becomes 0 or less, the underflow output terminal UNF transitions to "1". Selector 3
2A selects and outputs 0V when both the overflow output terminal OVF and the underflow output terminal UNF are "0", and selects and outputs the reference voltage VR when the overflow output terminal OVF is "1". When the flow output terminal UNF is "1", the reference voltage -VR is selected and output. When the sign bit SGN is "1", the AND gate 3
4 is closed, the AND gate 35 is opened, the conversion end signal EOC is supplied to the countdown input terminal D, and when the sign bit SGN is “0”, the AND gate 34 is opened and the AND gate 35 is closed. Conversion end signal EOC
Is supplied to the counter-up input terminal U.

The other points are the same as those in FIG.

In the above configuration, the signal AI0 is shown in FIG.
In the case of the waveform shown in (A), the sign bit SGN, the conversion end signal EOC, and the offset compensation voltage C are as shown in FIGS. 13 (B) to (D), respectively. That is, since the count value of the U / D counter 36 does not reach 32 while the sign bit SGN is "0", the selector 32A selects 0V, the offset adjustment does not work, and the problem shown in FIG. 10 occurs. Absent.

However, when the signal AI0 has a positive constant value as shown in FIG. 12A, the sign bit SG
N, the conversion end signal EOC, the offset compensation voltage C, and the signal AI are as shown in FIGS. That is, because the offset adjustment is weak, the signal AI
Takes a long time to converge to 0V.

[0013]

SUMMARY OF THE INVENTION In consideration of the above problems, an object of the present invention is to make it possible to converge the signal offset to 0 in a short time, and to obtain a normal signal waveform that does not include the offset. An object of the present invention is to provide an offset automatic adjustment circuit that can prevent deformation due to adjustment.

[0014]

FIG. 1 shows the principle configuration of an automatic offset adjusting circuit according to the present invention.

In the present invention, the output signal A is output by the offset compensation signal C corresponding to the code SGN of the output signal AI of the circuit 1.
In the offset automatic adjustment circuit for adjusting the offset of I, the difference k between the number of times the code SGN is positive and the number of times the code SGN is negative is substantially counted in synchronization with the clock φ, and the difference k is positive. Determination means 2 for determining whether or not the value is substantially equal to or more than the set value N or less than or equal to the negative set value-N, reference signal generation means 3 for outputting reference signals VR1 to VRn according to the result of the determination, and After it is determined that the difference k is substantially equal to or greater than the positive set value N or equal to or less than the negative set value −N,
When the inversion of the code SGN is detected, the difference k is substantially 0.
And an integrating means 5 that integrates the reference signals VR1 to VRn output from the reference signal generating means 3 and outputs the result as an offset compensation signal C in synchronization with the clock φ. ing.

In the present invention, the initialization means 4 makes the difference k substantially 0 immediately after it is judged that the difference k becomes substantially equal to or more than the positive set value N or equal to or less than the negative set value -N. However, when the inversion of the code SGN is detected, the difference k is set to substantially 0. Therefore, when the offset compensation operation is started, the offset compensation is performed at high speed, and the offset can be converged to 0 in a short time. . Further, since the determination unit 2 carefully determines whether or not the offset should be compensated before the offset compensation operation is started, it is possible to prevent the normal waveform that does not include the offset from being deformed by the offset adjustment.

In the first aspect of the present invention, in addition to the above configuration, the count value is cleared in response to the sign inversion detection, and it is determined that the difference k becomes equal to or more than the positive set value N or less than the negative set value -N. After that, before the inversion of the code SGN is detected, there is a counting means 6 for counting the clock φ one or more times, and the reference signal generating means 3 responds to the result of the above determination and the count value of the counting means 6. The reference signals VR1 to VRn are output.

According to this structure, when the offset of the output signal AI is relatively large, the offset compensation is more effectively performed when the offset compensation operation is started, and the offset can be converged to 0 in a shorter time.

In the third aspect of the present invention, the judging means 2 has an up / down counter 36A, and the count value of the up / down counter 36A overflows or underflows, so that the difference k is a positive set value N or more. Alternatively, the initialization unit 4 determines that the value becomes equal to or less than the negative set value −N and sets the average value PV of the count value that the up / down counter 36A overflows and the count value that underflows the underflow counter 36A to the up / down counter 36A. The difference k is made substantially zero.

In this case, since it is not necessary to separately provide a subtracter for obtaining the difference k and a comparator for determining that the difference k becomes equal to or more than the positive set value N or less than or equal to the negative set value -N, the configuration is simple. Become.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 2 shows an offset automatic adjustment circuit according to the first embodiment. The same components as those in FIG. 11 are designated by the same reference numerals and the description thereof will be omitted.

The automatic offset adjustment circuit 30B includes a U / D counter 36A and an initialization circuit 37A instead of the U / D counter 36 and the OR gate 37 of FIG.

The U / D counter 36A has a value PV = 16 set in the U / D counter 36A at the timing when the load control input terminal L transits from "1" to "0". It is different from the D counter 36.

The initialization circuit 37A includes an OR gate 371, an edge detection circuit 372, and an RS flip-flop 373.
Consists of. One of the two input terminals of the OR gate 371 is connected to the overflow output terminal OVF of the U / D counter 36A, the other is connected to the underflow output terminal UNF, and the output terminal thereof is connected to the set input terminal S of the RS flip-flop 373. Has been done. The edge detection circuit 372 is supplied with the sign bit SGN at its input end, and is connected at its output end to the reset input end R of the RS flip-flop 373. The output terminal Q of the RS flip-flop 373 is U /
It is connected to the load control input terminal L of the D counter 36A.

The other points are the same as those in FIG.

Next, the operation of the first embodiment constructed as described above will be explained.

The U / D counter 36A initially stores the value PV.
= 16 is set. Also, overflow output terminal O
The VF and the underflow output terminal UNF are both "0", the selector 32A outputs 0V, and the offset compensation voltage C output from the integrating circuit 31 is 0V.
In this state, signal AI is equal to signal AI0 without offset adjustment.

The signal vi is 0V and the signal AI0 is shown in FIG.
When it is a positive constant value as shown in (A), the sign bit SGN becomes "1" first, the AND gate 34 is closed and the AND gate 35 is opened, and the conversion as shown in FIG. The signal EOC passes through the AND gate 35 and becomes U /
It is supplied to the countdown input terminal D of the D counter 36A, and the count value of the U / D counter 36A is decremented.

When the count value of the U / D counter 36A becomes 0, the underflow output terminal UNF transits to "1", the reference voltage -VR is output from the selector 32A, and the constant value is output in synchronization with the conversion end signal EOC. The reference voltage −VR is integrated by the integrating circuit 31 for a short time, and the offset compensation voltage C changes as shown in FIG. On the other hand, when the underflow output terminal UNF changes to "1", the OR gate 3
The output of 71 becomes "1" and the RS flip-flop 37
The output terminal Q of 3 transits to "1" as shown in FIG.

When the signal AI is lowered by the offset compensation voltage C as shown in FIG. 3 (F) and the signal AI becomes a negative small value, the sign bit SGN transits to "0", and at this time,
One pulse is output from the edge detection circuit 372, and R
The output terminal Q of the S flip-flop 373 transits to "0". U / D at the timing of the fall of the potential at the output terminal Q
The value PV = 16 is set in the counter 36A, whereby the underflow output terminal UNF becomes "0" and the output of the selector 32A becomes 0V.

After this, the offset compensation voltage C and the signal A
I becomes constant, the AND gate 34 is opened, the AND gate 35 is closed, and the count value of the U / D counter 36A is incremented by the conversion end signal EOC. The overflow output terminal OVF transits to “1”, the RS flip-flop 373 is set on the one hand, and the output of the selector 32A becomes the reference voltage VR on the other hand, and the signal AI becomes a small positive value. Then, the sign bit SGN transits to "1", the RS flip-flop 373 is reset,
The value PV = 16 is set in the U / D counter 36A.

Thereafter, the operation in which the signal AI changes between positive and negative in the vicinity of 0 V is repeatedly performed.

As described above, the offset of the signal AI converges to 0V in a short time and becomes stable. Signal AI0 is shown in FIG.
In the case of the waveform as shown in FIG. 3 (A), the sign bit SG
N, the conversion end signal EOC, and the offset compensation voltage C are as shown in FIGS. 13B to 13D, and the offset adjustment can prevent the waveform of the signal AI having no offset from being deformed.

[Second Embodiment] FIG. 4 shows an automatic offset adjusting circuit according to a second embodiment. The same components as in FIG.
The same reference numerals are given and the description thereof is omitted.

This automatic offset adjustment circuit 30C uses a selector 32B instead of the selector 32A of FIG.
Further, the voltage dividing circuit 38 and the step counting circuit 39 are provided.

The voltage dividing circuit 38 is provided with a ladder resistor and outputs reference voltages 5VR, VR, 0, -VR and -5VR and supplies them to the selector 32B. Selector 32B is U / D
The logical values of the outputs from the overflow output terminal OVF and the underflow output terminal UNF of the counter 36A and the output of the step counting circuit 39 are in this order, 0V when (0,0,0), and a reference when (1,0,0) A voltage VR, a reference voltage 5VR when (1,0,1), a reference voltage -VR when (0,1,0), and a reference voltage -5VR when (0,1,1) are selected and output.

The step counting circuit 39 includes an AND gate 3
91 and an RS flip-flop 392.
The AND gate 391 has one of its two input terminals connected to the output terminal Q of the RS flip-flop 373, the other terminal supplied with the conversion end signal EOC, and its output terminal connected to the set input terminal S of the RS flip-flop 392. There is. In the RS flip-flop 392, the reset input terminal R is connected to the output terminal of the edge detection circuit 372, the output terminal Q is used as the output terminal of the step counting circuit 39, and the output terminal Q is connected to the control input terminal of the selector 32B. Has been done.

The other points are the same as those in FIG.

Next, the operation of the second embodiment constructed as described above will be explained.

Initially, the output of the selector 32B is 0V. As in the case of the first embodiment, the signal vi is 0V.
Then, when the signal AI0 has a positive constant value as shown in FIG. 5A, the conversion end signal EOC is decremented by the count value of the U / D counter 36A. The underflow output terminal UNF transits to "1", whereby the selector 32B outputs the reference voltage -VR on the one hand, and the reference voltage -VR is output by the integrating circuit 31 for a certain short time in synchronization with the conversion end signal EOC. Is integrated, and on the other hand, the output terminal Q of the RS flip-flop 373 is "1" as shown in FIG. 5 (C).
Then, the AND gate 391 is opened.

The next conversion end signal EOC is AND gate 3
The output terminal Q of the RS flip-flop 392 transits to '1' through 91, which causes the selector 32B to output the reference voltage -5VR, which is integrated by the integrating circuit 31 to obtain the offset compensation voltage C in FIG. ) Changes as shown in.

When the signal AI is lowered by the offset compensation voltage C as shown in FIG. 5 (F) and the signal AI becomes a negative value, the sign bit SGN transits to "0", and at this time, the edge detection circuit 372 outputs the signal. One pulse is output, and the output terminals Q of the RS flip-flops 373 and 392 transit to “0”. The value PV = 16 is set in the U / D counter 36A at the timing of the voltage drop of the output terminal Q, whereby the underflow output terminal UNF becomes "0" and the output of the selector 32B becomes 0V.

After this, the offset compensation voltage C and the signal A
I becomes constant, the AND gate 34 is opened, the AND gate 35 is closed, and the count value of the U / D counter 36A is incremented by the conversion end signal EOC. The overflow output terminal OVF transits to "1", whereby the RS flip-flop 373 is set on the one hand, and on the other hand, the output of the selector 32B becomes the reference voltage VR and the signal AI becomes a positive value. Then, the sign bit SGN transits to “1”, the RS flip-flop 373 is reset, and the value PV = 16 is set in the U / D counter 36A. At this time, the RS flip-flop 392 remains reset.

Thereafter, the operation in which the signal AI changes between positive and negative in the vicinity of 0 V is repeatedly performed.

As described above, when the offset of the signal AI0 is relatively large, this offset converges to 0V and stabilizes in a shorter time than in the first embodiment. Signal A
When I0 has a waveform as shown in FIG. 13A, the sign bit SGN, the conversion end signal EOC, and the offset compensation voltage C are shown in FIG. 13B as in the case of the first embodiment.
As shown in (D) to (D), the offset adjustment can prevent the signal waveform having no offset from being deformed.

[Third Embodiment] FIG. 6 shows an automatic offset adjusting circuit according to a third embodiment. The same components as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

This automatic offset adjustment circuit 30D has a selector 32C, a voltage dividing circuit 3 instead of the selector 32B, the voltage dividing circuit 38 and the step counting circuit 39 of FIG.
8A and a step counting circuit 39A are used.

The step counting circuit 39A uses a counter 392A instead of the RS flip-flop 392 which is a 1-bit counter in FIG. 4, and has a clock input terminal CK and a clear input terminal CLR of the counter 392A, respectively, and an output terminal and an AND gate 391. The output end of the edge detection circuit 372 is connected, and the count value of the counter 392A is selected by the selector 32.
It is supplied to the control input terminal of C.

On the other hand, the voltage dividing circuit 38A is provided with a ladder resistor and has reference voltages 6VR, 4VR, 2VR, VR, 0, -V.
R, -2VR, -4VR and -6VR are output and supplied to the selector 32C. The selector 32C includes a logical value of the output from the overflow output terminal OVF and the underflow output terminal UNF of the U / D counter 36A and the counter 39.
When the count value output of 2A is in this order, the reference voltage is 0 when (0,0,0), the reference voltage VR when (1,0,0), and the reference voltage 2VR when (1,0,1), (1, 0, 2) reference voltage 4VR, (1, 0, 3 or more) reference voltage 6VR, (0, 1, 0) reference voltage −VR, (0, 1, 1) reference voltage − When 2VR (0, 1, 2), the reference voltage -4VR (0, 1, 3 or more), the reference voltage -6VR is selected and output.

The signal vi is 0V and the signal AI0 is as shown in FIG.
As shown in FIG. 7B, changes in the sign bit SGN, the output terminal Q of the RS flip-flop 373, the conversion end signal EOC, the offset compensation voltage C, and the signal AI when the positive constant value is shown in FIG. It shows in (F). Since this change can be easily understood from the description of the second embodiment, the description thereof will be omitted.

In the third embodiment, when the offset of the signal AI0 is relatively large, this offset converges to 0 V and stabilizes in a shorter time than in the first embodiment. Signal A
When I0 has a waveform as shown in FIG. 13A, the sign bit SGN, the conversion end signal EOC, and the offset compensation voltage C are shown in FIG. 13B as in the case of the first embodiment.
As shown in (D) to (D), the offset adjustment can prevent the signal waveform having no offset from being deformed.

The present invention includes various modifications other than the above.

For example, the circuit 20 need only have an offset in its output, and is not necessarily the operational amplifier 21.
Does not have to be provided. Further, in the present invention, since the offset is adjusted according to the sign of the signal, the comparator may determine the sign instead of the A / D converter 10, and the signal may be used without being digitally converted. Circuit 20
If is a digital circuit, no A / D converter or comparator for detecting the code is required. In addition, U / D counter 3
Instead of 6A, two up counters or down counters, and a subtractor for calculating the difference between the count values of both counters,
You may use the structure provided with the comparator which compares the output of a subtractor with a setting value. The offset automatic adjustment circuit may use another clock instead of the conversion end signal EOC, and this clock does not necessarily have to be synchronized with the clock CLK. Further, for example, in FIG. 5, in place of the voltage dividing circuit 38A and the selector 32C, a current source that outputs a constant current and a gate circuit that supplies the current to the integrating circuit for a time corresponding to the control input signal are provided. The current may be integrated by the integrating circuit 31 to be converted into a voltage. Further, offset automatic adjustment circuits 30B to 30
The entire configuration of D (when the circuit 20 is a digital circuit) or a part thereof may be configured by a one-chip microcomputer.

[0055]

As described above, according to the offset automatic adjustment circuit of the present invention, the difference k between the number of times the sign SGN of the signal is positive and the number of times the sign is negative is a positive set value N.
When it is determined that the difference k is substantially equal to or more than or equal to or less than the negative set value -N, the difference k is not set to substantially 0 immediately, but when the inversion of the code SGN is detected, the difference k is set to substantially 0. Therefore, when the offset compensation operation is started, the offset compensation is performed at a high speed, and the offset of the output signal of the analog circuit can be converged to 0 in a short time. Further, the determination means determines the offset before the offset compensation operation is started. Since it is carefully determined whether or not to compensate, it has an excellent effect that it can prevent the normal waveform that does not include the offset from being deformed by the offset adjustment, and largely contributes to the improvement of the signal quality. .

According to the first aspect of the present invention, when the offset of the signal is relatively large, the offset compensation is more effectively performed when the offset compensation operation is started, and the offset can be converged to 0 in a shorter time. It has the effect of being able to.

According to the third aspect of the present invention, the subtractor for obtaining the difference k and the difference k are equal to or greater than the positive set value N or the negative set value -N.
Since it is not necessary to separately provide a comparator that determines that the following, it is possible to simplify the configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a principle configuration of the present invention.

FIG. 2 is a circuit diagram of an offset automatic adjustment circuit according to the first embodiment of the present invention.

FIG. 3 is a waveform chart showing the operation of the circuit of FIG.

FIG. 4 is a circuit diagram of an offset automatic adjustment circuit according to a second embodiment of the present invention.

5 is a waveform chart showing the operation of the circuit of FIG.

FIG. 6 is a circuit diagram of an offset automatic adjustment circuit according to a third embodiment of the present invention.

7 is a waveform chart showing the operation of the circuit of FIG.

FIG. 8 is a conventional offset automatic adjustment circuit diagram.

9 is a waveform chart showing the operation of the circuit of FIG.

10 is a waveform chart showing the operation of the circuit of FIG.

FIG. 11 is another conventional offset automatic adjustment circuit diagram.

12 is a waveform chart showing the operation of the circuit of FIG.

13 is a waveform chart showing the operation of the circuit of FIG.

[Explanation of symbols]

 10 A / D converter 20 Circuit 21 Operational amplifier 22 Offset compensation circuit 30, 30A-30D Automatic offset adjustment circuit 31 Integration circuit 32, 32A-32C Selector 36, 36A U / D counter 37A Initialization circuit 372 Edge detection circuit 373, 392 RS flip-flop 38, 38A voltage dividing circuit 39 step counting circuit 392A counter

Claims (3)

[Claims] 1. An automatic offset adjustment circuit for adjusting an offset of an output signal (AI) of a circuit (1) by an offset compensation signal (C) corresponding to a sign (SGN) of the output signal (AI), in synchronization with a clock (φ). Then, the difference k between the number of times the sign is positive and the number of times the sign is negative is substantially counted, and the difference k is substantially greater than or equal to the positive set value N or less than or equal to the negative set value −N. Determining means (2) for determining whether or not the reference signal generating means (3) outputs reference signals (VR1 to VRn) according to the result of the determination, and the difference k is a positive set value N or more, or After it is determined that the value has become substantially equal to or less than the negative set value -N, when the inversion of the sign is detected, an initialization unit (4) for setting the difference k to substantially 0 and synchronization with the clock. The reference signal output from the reference signal generating means, and integrates the result. An automatic offset adjusting circuit, comprising: an integrating means (5) for outputting as an offset compensation signal. 2. A counter value is cleared in response to the sign inversion detection, and the difference k is equal to or greater than a positive set value N or a negative set value −.
After it is determined that the number is substantially equal to or less than N and before the inversion of the sign is detected, the clock signal (φ) includes a counting unit (6) that counts one or more times, and the reference signal generation unit ( 3) is a reference signal (VR1 to VRn) corresponding to the result of the determination and the count value of the counting means.
The offset automatic adjustment circuit according to claim 1, wherein 3. The determination means (2) has an up-down counter (36A), and the difference k is a positive set value N or more because the count value of the up-down counter overflows or underflows. Alternatively, the initialization means (4) determines the average value (PV) of the count value at which the up-down counter overflows and the count value at which the up-down counter overflows as a negative set value-N or less, and the up-down counter. 3. The automatic offset adjustment circuit according to claim 1, wherein the difference k is set to be substantially zero by setting the difference k to 0.