JPS6342209A - Digital control type automatic gain control unit - Google Patents

Abstract

PURPOSE:To increase a leading-in speed, and also, to execute an automatic gain control being strong against the noise, by constituting the titled unit so that an up/down counter for coefficient can be operated from the upper bit. CONSTITUTION:The titled unit is provided with an up/down repetition detecting circuit 4 for generating a pulse, when an output of a random walk filter 2 has repeated up/down I times, an up/down counter 7 which has provided a count enable terminal on output bits, respectively, a down-counter 5 for executing count-down, whenever a pulse of the detecting circuit is sent out, and a decoder 6 for decoding a down-count value to a control signal to an enable terminal of the up/down counter. In this way, the enable terminal of every output bit of the up/down counter 7 is made enable from the upper bit, whenever the output of the random walk filter 2 has repeated up/down I times continuously. Accordingly, the up/down counter for coefficient is updated from the upper bit side, and the convergence speed can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a lock circuit diagram related to a digitally controlled automatic gain control (hereinafter referred to as AGC) device for a programmable gain amplifier having, for example, numerical gain steps. In the figure, (1) is an up/down determination circuit (not shown) that receives an output signal from a programmable gain amplifier and determines whether the value of the signal is larger or smaller than a set level;
(2) is a random walk filter that sends out an up signal when the difference between the number of up and down times is larger than a predetermined value, and sends out a down signal when the difference is smaller than a negative predetermined value, and (3) is a random walk filter. Walk filter (2)
) is an up/down counter for coefficients that sends coefficient control signals through digital control to the programmable gain amplifier based on up and down signals from QA. MSB) has t up to Qε.

The operation in the above configuration will be explained. First, when the output signal of the programmable gain amplifier is input to the input terminal of the amplifier down determination circuit (1), it determines whether the gain should be increased or decreased relative to the desired level, and outputs the up/down determination circuit. is input into the up-down input of the random walk filter (2). In the random walk filter (2), the number of times it is determined to be up with respect to a predetermined constant value is M, and the number of times it is determined to be down is N, and if M-N>L, the gain to the programmable gain amplifier is Increase the coefficient by one and also set M-N<-
If it is L, a signal that lowers the gain coefficient by one is output to the coefficient up/down counter (3), and this up/down counter (3) outputs the coefficient control signal to the programmable gain amplifier, that is, the lowest pitch. )L
A coefficient control signal that changes sequentially from SB to MSB is sent out.

[Problem that the invention seeks to solve]

In conventional digitally controlled AGC devices, the output of the random walk filter (2) is configured to change values sequentially starting from the lowest bit (LSB) of the coefficient up/down counter (3). There was a problem that it took a long time for the changes to be made.

The present invention was made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a digitally controlled AGC device that can control an input signal to a desired level and can pull the input signal to the desired level in a short time. With the goal.

[Means for solving problems]

The digitally controlled automatic gain control device according to the present invention includes an up-down repeat detection circuit that generates a pulse when the random walk filter output repeats up-down once, and an up-down repeat detection circuit that generates a pulse when the output of the random walk filter is repeated once, and a count enable terminal provided for each output bit. The device includes a counter, a down counter that counts down every time the detection circuit sends out a pulse, and a decoder that decodes the down count value into a control signal sent to an enable terminal of the up/down counter.

[Effect]

The digitally controlled automatic gain control device in this invention includes:
By enabling the enable terminal for each output bit of the up-down counter starting from the upper bits each time the output of the random walk filter continues to go up and down, the up-down counter for coefficients is updated from the upper bit side. This allows for faster convergence.

(Example) Hereinafter, an example of the present invention will be explained with reference to the drawings.
In the figure, (1) is an up/down determination circuit that determines whether the output signal of the programmable gain amplifier is higher or lower than a desired level, (2) is a predetermined constant value L, and M is the number of ups. , when the number of down signals is N, if M-N>L, then up signal; if M-N<-L,
Random walk filter that outputs a down signal (4
) is an up/down repetition detection circuit that outputs a pulse when the random walk filter output repeats up/down once, (5) is a down counter that counts down every time a pulse is received from the detection circuit (4), (6) takes the value of counter (5) as input.

A decoder outputs an enable signal to an up/down counter (8), and (8) is a random walk filter (
This is an up/down counter that uses the up/down signal output of 2) as input, the output of the decoder (6) as an enable signal input for each bit of the counter, and the counter output as a coefficient control signal to the programmable gain amplifier.

FIG. 2 is a waveform diagram showing the main signals in FIG. 1. In Figure 2, waveform (a) is the waveform (a) of the up/down determination circuit (
1), and the waveform CIl+) is the clock CLK input to the random walk filter (2).
The waveform (C) is the up-down judgment output of the up-down judgment circuit (1), the waveform (d) is the clock output of the random walk filter (2), and the waveform (e
) is the pulse output of the up-down repetition detection circuit (4), and the waveform (f).

(g), (h), (i), and (j) are the waveforms from MSB to LSB of the output to the programmable gain amplifier of the coefficient up/down counter, respectively.

Now, in FIG. 2, the peak of waveform (a) exists at the rising edge of Ti (1≦f≦18). Also,
It is assumed that the coefficient up/down counter is changed at the falling edge of the period Ti.

First, the random walk filter (2) is a random walk filter with two stages, and the down counter (5) is
It is set to the same value as the output bit width of the coefficient up/down counter. At this time, the decoder (6) selects the most significant bit (MSB) of the coefficient up-grain counter (7).
) is enabled so that only the down counter (5)
decoding the output of Up/down judgment circuit (1
), when the waveform (a) is input to the input signal, it is compared with the desired peak level, and since the input signal is smaller in the period T1, the up/down judgment circuit (1) moves in the direction of increasing the gain, that is, in the direction of increasing the gain. outputs the up signal to the random walk filter (2) as a determination result output. Since the internal counter of the random walk filter (2) is reset to O, it is only incremented to +1 and no overflow output occurs.

Next, since the input signal with period T2 has the same magnitude as the input signal with period TI, the counter inside the random walk filter (2) is incremented as in the case of period T1. The counter becomes +2, so Opafuo
- At cycle MT2 of waveform (d), the random walk filter output clock is input to the coefficient up/down counter (7).

The enable terminal of the coefficient up/down counter (7) remains in its initial state and only the MSB is enabled.

An up signal is input to the up/down input terminal. Since there is a clock input at this time, the MSB is incremented from 0 to 1, and the gain is set from 2 to 18.

In period T3, M of the coefficient up/down counter (7)
Since this is after SB has been incremented, the input signal of waveform (a) is thicker than the desired peak level.

At this time, the up/down determination circuit (RI) outputs a down signal to the random walk filter (2). Since the random walk filter (2) has output an overflow, it is reset to O, so the internal counter is Decremented from O to -1.

In period T4, the internal counter of the random walk filter (2) is decremented from -1 to 12 in the same manner as in period T3. At this time, the counter becomes -2, so there is an underflow output.

When there is an output from the random walk filter, the up/down repetition detection circuit (3) increments an internal counter if it overflows and then underflows, or if it underflows and then overflows. If there is an underflow or an overflow after an overflow, the counter is reset to O, and when the counter reaches a certain threshold value (in this case, 2 times), a pulse is output. Therefore, this pulse decrements the counter value 5 of the down counter (5), and the counter value becomes 4.

At this time, the decoder (6) had previously enabled only Eε of the enable terminal of the up/down counter with coefficient enable (7), but it now enables EC to Eε.

When the random walk filter (2) outputs a down signal at a period of 8, the QD of the up/down counter (7) with coefficient enable changes, and the counter value changes from 18 to 1O.

As described above, the down counter (5) counts down until the enable terminal of the coefficient enable up/down counter (7) becomes enabled for all from MSB to LSB.

In this way, values up to the LSB are determined.

〔Effect of the invention〕

As described above, according to the present invention, since the coefficient up/down counter can be operated from the upper bits, the AG
The drawing speed of C is also fast, and it has the effect of being resistant to noise.

[Brief explanation of drawings]

FIG. 1 shows a digitally controlled AG according to an embodiment of the present invention.
2(a) to 2(j) are waveform diagrams illustrating the operation of each part of the above embodiment. FIG. 3 is a configuration diagram showing a conventional digitally controlled AGC circuit. (1) is an up-down judgment circuit, (2) is a random walk filter, (4) is an up-down repetition detection circuit, (5) is a down counter, (6) is a decoder, and (7) is an up-down with coefficient enable. down counter. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] An up/down determination circuit that determines whether the value of the input signal is greater than or less than a set level, and sends out an up signal when the difference between the number of up and down times is greater than a predetermined value;
A random walk filter that sends out a down signal when the difference is smaller than a predetermined negative value; an up-down repeat detection circuit that outputs a pulse when the filter output is up and the sending of the down signal is repeated a predetermined number of times; A down counter that counts down every time a pulse is sent, a decoder that sends out an enable signal based on the input of the count value of the counter, and a gain that receives the up and down signals from the random walk filter and the enable signal for each bit from the decoder as input. A digitally controlled automatic gain control device comprising an up/down counter that outputs a coefficient control signal by digitally controlling an amplifier.