KR970024591A - Noise reduction circuit - Google Patents

Noise reduction circuit Download PDF

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Publication number
KR970024591A
KR970024591A KR1019950035086A KR19950035086A KR970024591A KR 970024591 A KR970024591 A KR 970024591A KR 1019950035086 A KR1019950035086 A KR 1019950035086A KR 19950035086 A KR19950035086 A KR 19950035086A KR 970024591 A KR970024591 A KR 970024591A
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KR
South Korea
Prior art keywords
signal
detection circuit
noise
circuit
output signal
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Application number
KR1019950035086A
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Korean (ko)
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KR0177756B1 (en
Inventor
송웅호
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김광호
삼성전자 주식회사
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Priority to KR1019950035086A priority Critical patent/KR0177756B1/en
Publication of KR970024591A publication Critical patent/KR970024591A/en
Application granted granted Critical
Publication of KR0177756B1 publication Critical patent/KR0177756B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Noise Elimination (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야; 본 발명은 반도체 메모리 장치나 전기회로장치의 노이즈제거회로에 관한 것이다.1. the technical field to which the invention described in the claims belongs; The present invention relates to a noise removing circuit of a semiconductor memory device or an electric circuit device.

2. 발명이 해결하려고 하는 기술적 과제; 본 발명은 종래기술에 의한 지연된 신호를 기존의 논리적 합성을 벗어나 입력신호의 라이징과 폴링시 일정시간지연을 통하여 입력신호의 상태를 검색하여 상기 입력신호를 합성하여 노이즈를 제거하는 노이즈제거회로를 제거한다.2. The technical problem to be solved by the invention; The present invention removes a noise removing circuit for synthesizing the input signal to remove the noise by retrieving the state of the input signal through a predetermined time delay during rising and polling of the input signal out of the conventional logical synthesis of the delayed signal according to the prior art. do.

3. 발명의 해결방법의 요지; 본 발명은 외부에서 입력되는 소정의 입력신호를 응답하여 노이즈를 제거한 일정한 레벨의 출력신호를 출력하는 노이즈제거회로에 있어서, 상기 입력신호에 응답하여 일정레벨의 신호를 출력하는 입력버퍼와, 상기 입력버퍼의 출력신호에 응답하여 상기 출력신호의 라이징시점에 따라 동시에 라이징된 신호를 출력하고 노이즈를 제거하기 위한 라이징검출회로와, 상기 라이징검출회로와 병렬접속되며 상기 입력버퍼의 출력신호에 응답하여 상기 출력신호의 폴링시점에 따라 동시에 폴링된 신호를 출력하고 노이즈를 제거하기 위한 폴링검출회로와, 상기 라이징검출회로 및 폴링검출회로의 출력단에 병렬로 접속되어 상기 라이징검출회로 및 폴링검출회로의 출력신호를 입력으로 하여 논리조합하여 완전히 노이즈가 제거된 출력신호를 출력하는 신호합성회로를 포함한다.3. Summary of the Solution of the Invention; According to an aspect of the present invention, there is provided a noise canceling circuit for outputting a constant level output signal from which noise is removed in response to a predetermined input signal input from an external device, comprising: an input buffer for outputting a predetermined level signal in response to the input signal; A rising detection circuit for simultaneously outputting a risen signal and removing noise according to a rising point of the output signal in response to an output signal of a buffer; and a parallel connection with the rising detection circuit and in response to the output signal of the input buffer A polling detection circuit for outputting a polled signal and removing noise at the same time according to a polling time of an output signal, and an output signal of the rising detection circuit and the polling detection circuit connected in parallel to the output terminals of the rising detection circuit and the falling detection circuit; To output an output signal with total noise removed by logical combination And a combining circuit.

4. 발명의 중요한 용도; 반도체 메모리 장치 또는 전기회로장치에 적합하게 사용된다.4. Significant use of the invention; It is suitably used for a semiconductor memory device or an electric circuit device.

Description

노이즈제거회로Noise reduction circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 노이즈제거회로의 기능블럭도,2 is a functional block diagram of a noise removing circuit according to the present invention;

제3도는 본 발명에 따른 실시예로서 노이즈제거회로의 구체적인 회로도.3 is a detailed circuit diagram of a noise removing circuit as an embodiment according to the present invention.

Claims (6)

외부에서 입력되는 소정의 입력신호에 응답하여 노이즈를 제거한 일정한 레벨의 출력신호를 출력하는 노이즈 제거회로에 있어서, 상기 입력신호에 응답하여 일정레벨의 신호를 출력하는 입력버퍼와, 상기 입력버퍼의 출력신호에 응답하여 상기 출력신호의 라이징시점에 따라 동시에 라이징된 신호를 출력하고 노이즈를 제거하기 위한 라이징검출회로와, 상기 라이징검출회로와 병렬접속되며 상기 입력버퍼의 출력신호에 응답하여 상기 출력신호의 폴링시점에 따라 동시에 폴링된 신호를 출력하고 노이즈를 제거하기 위한 폴링검출회로와, 상기 라이징검출회로 및 폴링검출회로의 출력단에 병렬로 접속되어 상기 라이징검출회로 및 폴링검출회로의 출력신호를 입력으로 하여 논리조합하여 완전히 노이즈가 제거된 출력신호를 출력하는 신호합성회로를 구비함을 특징으로 하는 노이즈제거회로.A noise removing circuit for outputting a constant level output signal from which noise is removed in response to a predetermined input signal input from an external device, comprising: an input buffer for outputting a signal of a predetermined level in response to the input signal, and an output of the input buffer A rising detection circuit for simultaneously outputting a raised signal and removing noise in response to the rising time of the output signal in response to the signal; and a parallel connection with the rising detection circuit, the output signal in response to an output signal of the input buffer A polling detection circuit for outputting a signal polled at the same time as the polling time and removing noise, and connected in parallel to the output terminals of the rising detection circuit and the falling detection circuit and receiving the output signals of the rising detection circuit and the falling detection circuit as inputs. Synthesizing the output signal with total noise removed by logical combination A noise reduction circuit which is characterized by comprising. 제1항에 있어서, 상기 입력버퍼가 히스테리시스 입력버퍼임을 특징으로 하는 노이즈제거회로.The noise canceling circuit of claim 1, wherein the input buffer is a hysteresis input buffer. 제1항에 있어서, 상기 라이징검출회로가 리셋디이플립플롭회로로 구성함을 특징으로 하는 노이즈제거회로.The noise canceling circuit according to claim 1, wherein said rising detection circuit comprises a reset dip flip-flop circuit. 제1항에 있어서, 상기 폴링검출회로가 세트디이플립플롭회로로 구성함을 특징으로 하는 노이즈제거회로.The noise canceling circuit according to claim 1, wherein said polling detection circuit comprises a set dip flip-flop circuit. 제1항에 있어서, 상기 라이징검출회로 및 폴링검출회로가 초기화회로를 더 구비하여 구성함을 특징으로 하는 노이즈제거회로.The noise canceling circuit according to claim 1, wherein the rising detection circuit and the falling detection circuit further comprise an initialization circuit. 제1항에 있어서, 상기 신호합성회로가 앤드게이트로 구성함을 특징으로 하는 노이즈제거회로.The noise canceling circuit according to claim 1, wherein said signal synthesizing circuit comprises an AND gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950035086A 1995-10-12 1995-10-12 Noise eliminating circuit KR0177756B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950035086A KR0177756B1 (en) 1995-10-12 1995-10-12 Noise eliminating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950035086A KR0177756B1 (en) 1995-10-12 1995-10-12 Noise eliminating circuit

Publications (2)

Publication Number Publication Date
KR970024591A true KR970024591A (en) 1997-05-30
KR0177756B1 KR0177756B1 (en) 1999-04-01

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KR1019950035086A KR0177756B1 (en) 1995-10-12 1995-10-12 Noise eliminating circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437622B1 (en) * 1997-06-23 2004-09-04 주식회사 하이닉스반도체 Input circuit including glitch protection circuit

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