KR970067690A - 고밀도 플라즈마 막의 고유 스트레스를 감소하기 위한 방법 및 그 장치 - Google Patents

고밀도 플라즈마 막의 고유 스트레스를 감소하기 위한 방법 및 그 장치 Download PDF

Info

Publication number
KR970067690A
KR970067690A KR1019970011024A KR19970011024A KR970067690A KR 970067690 A KR970067690 A KR 970067690A KR 1019970011024 A KR1019970011024 A KR 1019970011024A KR 19970011024 A KR19970011024 A KR 19970011024A KR 970067690 A KR970067690 A KR 970067690A
Authority
KR
South Korea
Prior art keywords
plasma
layer
film
substrate
semiconductor substrate
Prior art date
Application number
KR1019970011024A
Other languages
English (en)
Other versions
KR100277609B1 (ko
Inventor
브이. 라비 케이.
로스만 켄트
사힌 터것
나반카 프라빈
Original Assignee
조셉 제이. 스위니
어플라이드 머티어리얼스. 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 조셉 제이. 스위니, 어플라이드 머티어리얼스. 인코포레이티드 filed Critical 조셉 제이. 스위니
Publication of KR970067690A publication Critical patent/KR970067690A/ko
Application granted granted Critical
Publication of KR100277609B1 publication Critical patent/KR100277609B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C23C16/402—Silicon dioxide
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/517—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using a combination of discharges covered by two or more of groups C23C16/503 - C23C16/515
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

감소된 스트레스의 층은 유도 결합된 RF 에너지의 응용을 지연 또는 중단함으로써 HDP-CVD 시스템을 사용하여 기판 상에 형성된다. 상기 층은 HDP 시스템 챔버내에 처리 가스를 유입하고 유도 코일에 대한 RF 전력의 응용에 의해 처리 가스로부터 플라즈마를 형성함으로써 형성된다. 선택된 주기 후, 상기 막의 제 2 층은 유도 결합된 플라즈마를 유지하고 상기 플라즈마의 스퍼터링 효과를 증진하기 위해 상기 기판을 향해 상기 플라즈마를 바이어싱 함으로써 증착된다. 바람직한 실시예에서, 상기 증착된 막은 산화 실리콘막이고, 바이어싱은 바람직하게 RF 발생기로부터 시일링 플레이트 전극과 웨이퍼 지지용 전극까지의 유도 결합된 RF 전력의 응용에 의해 수행된다.

Description

고밀도 플라즈마 막의 고유 스트레스를 감소하기 위한 방법 및 그 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도 1은 본 발명에 따른 간략화된 HDP-CVD 장치의 한 실시예의 수직 단면도.

Claims (10)

  1. 처리 챔버내에 배치된 기판 상에 막을 증착하는 방법에 있어,
    (a) 상기 처리 챔버내에 처리가스를 유입하는 단계와;
    (b) 상기 처리 가스로부터 플리즈마를 형성하여 제 1 시간 주기 동안 상기 기판 상에 상기 막의 제 1 층을 증착하기 위해 유도 결합된 코일에 RF 전력을 인가하는 단계와;
    (C) 상기 제 1 시간 주기 다음의 제 2시간 주기 동안 상기 플라즈마를 유지하고, 상기 플라즈마의 스퍼터링 효과를 증진하고 상기 제 1 층 상에 상기 막의 제 2 층을 증착하도록 상기 기판을 향해 상기 플라즈마를 바이어싱하는 단계를 포함하는 막 증착 방법.
  2. 제 1항에 있어서, 상기 바이어싱 단계는 정전 결합된 전극에 RF 전력을 인가함으로써 수행되는 것을 특징으로 하는 막 증착 방법.
  3. 제 1항에 있어서, 상기 제 2 시간 주기는 상기 제 1 시간 주기 보다 적어도 10번 더 긴것을 특징으로 하는 막 증착 방법.
  4. 제 1항에 있어서, 상기 처리 가스는 실리콘과 산소를 포함하여, 상기 증착된 막은 산화 실리콘막인 것을 특징으로 하는 막 증착 방법.
  5. 제 2항에 있어서, 상기 정전적 결합 전극에 대한 RF 전력의 응용은 상기 유전적 결합 전극에 대한 RF 전력의 응용이 유지되는 동안 약 1 내지 100초 지연되는 것을 특징으로 하는 막 증착 방법.
  6. 제 1항에 있어서, 상기 제 1 층은 상기 제 2 층이 증착되는 두께의 약 1 내지 15 퍼센트 두께로 증착되는 것을 특징으로 하는 막 증착 방법.
  7. 고밀도 플라즈마 화학 기상 증착 시스템에 있어서, 전공 챔버를 형성하기 위한 하우징과; 상기 진공 챔버를 비우기 위한 진공 펌프와; 반도체 기판을 홀딩하기 위해 상기 하우징내에 배치되는 지지대와; 상기 진공 챔버내로 처리 가스를 유입하기 위한 가스 분배 장치와; 상기 진공 챔버내의 상기 처리 가스로부터 유도적 결합 플라즈마를 형성하고 플라즈마를 강화하기 위해 상기 기판을 향해 상기 플라즈마를 바이어싱하기 위한 플라즈마 발생 장치와; 상기 진공 펌프, 상기 가스 분배 장치 및 상기 플라즈마 발생 장치를 제어하기 위한 제어기와; 상기 제어기에 결합되고 상기 장치의 작동을 명령하기 위한 프로그램을 저장하는 메모리를 포함하며, 상기 프로그램은, 상기 챔버내로 상기 처리 가스를 유입하도록 상기 가스 분배 장치를 제어하는 제 1 단계와; 상기 처리 가스로부터 플라즈마를 형성하고 상기 기판 상에 상기 막의 제 1층을 증착하기 위해 상기 유도적 결합 코일에 RF 전력을 인가하도록 상기 프라즈마 발생 장치를 제어하는 제 2단계와; 상기 유도적 결합 플라즈마를 유지하고 상기 기판을 향해 상기 플라즈마를 바이어싱하도록 상기 플라즈마 발생 장치를 제어햐여 상기플라즈마의 스퍼터링 효과를 증진시키고 상기 막의 제 2층을 증착하는 제 3 단계에 의해 스트레스 감소된 막을 증착하기 위한 한 세트의 명령을 포함하는 것을 특징으로 하는 고밀도 플라즈마 화학 기상 증착 시스템.
  8. 제 7항에 있어서, 상기 프로그램은, 상기 유도적 결합 플라즈마를 유지하고 상기 기판을 향한 상기 플라즈마의 바이어싱을 중단하기 위해 상기 플라즈마 발생 장치를 제어하는 제 4단계와; 다섯째, 상기 유도적 결합 플라즈마를 유지하고 상기 기판을 향해 플라즈마를 바이어싱하기 위해 상기 플라즈마 발생 장치를 제어하여 상기 플라즈마의 스퍼터링 효과를 증진하는 제 5단계와; 여섯째, 상기 막의 요구된 두께가 얻어질 때까지 적어도 한번 반복적으로 상기 제 2 단계와 상기 제 3단계를 수행하는 제 6 단계에 의해 다수의 상기 제 1 층과 상기 제 2 층을 증착하기 위한 명령을 더 포함하는 것을 특징으로 하는 고밀도 플라즈마 화학 기상 증착 시스템.
  9. 반도체 기판상에 형성되는 집적 회로에 있어서,
    (a) 상기 반도체 기판내에 형성되는 다수의 능동 소자와;
    (b) 상기 반도체 기판 상에 형성되는 적어도 하나의 금속층과;
    (c) 상기 금속층과 반도체 기판 사이에 형성되는 적어도 하나의 절연층을 포함하고, 상기 절연층은 상기 반도체 기판의 선택된 부분에 대해 상기 금속층의 선택된 부분에 전기적으로 접촉되도록 전기적 도전 재료로 채워지는 다수의 패턴화된 홀을 가지고, 상기 절연층은 제 1 산화 실리콘층과 제 2 산화 실리콘층을 포함하고, 상기 제 1 및 제 2 산화 실리콘층을 고밀도 플라즈마 화학 기상 증착 공정을 사용하여 증착되며, 상기 제 1 산화 실리콘층은 상기 제 2 산화 실리콘내의 기계적 스트레스의 감소를 위해 증착되는 것을 특징으로 하는 집적 회로,
  10. 제 9항에 있어서,
    (a) 상기 반도체 기판 위와 상기 적어도 하나의 절연층 아래에 형성되는 제 2 금속층과;
    (b) 상기 제 2 금속층과 상기 반도체 기판 사이에 형성되는 제 2 절연층을 포함하고, 상기 제 2 절연층은 상기 다수의 능동 소자의 선택된 영역에 대해 상기 제 2 금속층의 선택된 부분에 전기적으로 접촉하도록 전기적 도전 재료로 채워지는 다수의 제 2 패턴화된 홀을 가지는 것을 특징으로 하는 집적 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970011024A 1996-03-28 1997-03-28 고밀도 플라즈마 막의 고유 스트레스를 감소하기 위한 방법 및 그 장치 KR100277609B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/623,445 US5976993A (en) 1996-03-28 1996-03-28 Method for reducing the intrinsic stress of high density plasma films
US8/623,445 1996-03-28
US08/623,445 1996-03-28

Publications (2)

Publication Number Publication Date
KR970067690A true KR970067690A (ko) 1997-10-13
KR100277609B1 KR100277609B1 (ko) 2001-02-01

Family

ID=24498118

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970011024A KR100277609B1 (ko) 1996-03-28 1997-03-28 고밀도 플라즈마 막의 고유 스트레스를 감소하기 위한 방법 및 그 장치

Country Status (3)

Country Link
US (2) US5976993A (ko)
JP (1) JP3927642B2 (ko)
KR (1) KR100277609B1 (ko)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1387394A3 (en) * 1997-04-15 2004-04-07 STMicroelectronics S.r.l. Process of final passivation of integrated circuit devices
JP3141827B2 (ja) 1997-11-20 2001-03-07 日本電気株式会社 半導体装置の製造方法
US6759306B1 (en) * 1998-07-10 2004-07-06 Micron Technology, Inc. Methods of forming silicon dioxide layers and methods of forming trench isolation regions
US6271112B1 (en) * 1998-11-13 2001-08-07 Advanced Micro Devices, Inc. Interlayer between titanium nitride and high density plasma oxide
US6225210B1 (en) * 1998-12-09 2001-05-01 Advanced Micro Devices, Inc. High density capping layers with improved adhesion to copper interconnects
US6583069B1 (en) * 1999-12-13 2003-06-24 Chartered Semiconductor Manufacturing Co., Ltd. Method of silicon oxide and silicon glass films deposition
US6500771B1 (en) 2000-01-31 2002-12-31 Chartered Semiconductor Manufacturing Ltd. Method of high-density plasma boron-containing silicate glass film deposition
US6355581B1 (en) 2000-02-23 2002-03-12 Chartered Semiconductor Manufacturing Ltd. Gas-phase additives for an enhancement of lateral etch component during high density plasma film deposition to improve film gap-fill capability
US6450117B1 (en) 2000-08-07 2002-09-17 Applied Materials, Inc. Directing a flow of gas in a substrate processing chamber
US6803222B2 (en) * 2000-11-22 2004-10-12 Kao Corporation Alkaline proteases
US6531412B2 (en) * 2001-08-10 2003-03-11 International Business Machines Corporation Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications
US6676760B2 (en) 2001-08-16 2004-01-13 Appiled Materials, Inc. Process chamber having multiple gas distributors and method
US6541370B1 (en) 2001-09-17 2003-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Composite microelectronic dielectric layer with inhibited crack susceptibility
US7067439B2 (en) 2002-06-14 2006-06-27 Applied Materials, Inc. ALD metal oxide deposition process using direct oxidation
US6768828B2 (en) * 2002-11-04 2004-07-27 Little Optics Inc. Integrated optical circuit with dense planarized cladding layer
US7786021B2 (en) * 2002-11-14 2010-08-31 Sharp Laboratories Of America, Inc. High-density plasma multilayer gate oxide
US6828255B2 (en) 2002-11-22 2004-12-07 Taiwan Semiconductor Manufacturing Co., Ltd Crack inhibited composite dielectric layer
US7300829B2 (en) * 2003-06-02 2007-11-27 Applied Materials, Inc. Low temperature process for TFT fabrication
US6914015B2 (en) * 2003-10-31 2005-07-05 International Business Machines Corporation HDP process for high aspect ratio gap filling
US6949460B2 (en) * 2003-11-12 2005-09-27 Lam Research Corporation Line edge roughness reduction for trench etch
US8119210B2 (en) 2004-05-21 2012-02-21 Applied Materials, Inc. Formation of a silicon oxynitride layer on a high-k dielectric material
US20060105114A1 (en) * 2004-11-16 2006-05-18 White John M Multi-layer high quality gate dielectric for low-temperature poly-silicon TFTs
KR100665846B1 (ko) * 2005-01-21 2007-01-09 삼성전자주식회사 반도체 소자 제조를 위한 박막 형성방법
US7645710B2 (en) 2006-03-09 2010-01-12 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7837838B2 (en) 2006-03-09 2010-11-23 Applied Materials, Inc. Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus
US7678710B2 (en) 2006-03-09 2010-03-16 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
CN101460659B (zh) * 2006-06-02 2011-12-07 应用材料股份有限公司 利用压差测量的气流控制
JP5590886B2 (ja) 2006-09-26 2014-09-17 アプライド マテリアルズ インコーポレイテッド 欠陥パシベーションのための高ｋゲート積層構造に対するフッ素プラズマ処理
US9137884B2 (en) 2006-11-29 2015-09-15 Lam Research Corporation Apparatus and method for plasma processing
US20080157292A1 (en) * 2006-12-29 2008-07-03 Texas Instruments Inc. High-stress liners for semiconductor fabrication
US7805258B2 (en) * 2007-02-16 2010-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for film stress and curvature gradient mapping for screening problematic wafers
JP5203758B2 (ja) * 2008-03-17 2013-06-05 東京エレクトロン株式会社 プラズマ処理装置
JP5374935B2 (ja) * 2008-06-23 2013-12-25 セイコーエプソン株式会社 Ｃｖｄ装置及び半導体装置の製造方法
KR20130063564A (ko) * 2011-12-07 2013-06-17 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US20140186544A1 (en) * 2013-01-02 2014-07-03 Applied Materials, Inc. Metal processing using high density plasma
US20160329206A1 (en) * 2015-05-08 2016-11-10 Lam Research Corporation Methods of modulating residual stress in thin films
US12062537B2 (en) 2019-03-25 2024-08-13 Lam Research Corporation High etch selectivity, low stress ashable carbon hard mask
KR20220084394A (ko) 2019-10-25 2022-06-21 어플라이드 머티어리얼스, 인코포레이티드 고품질 pvd 막들을 증착하기 위한 방법
WO2021108294A2 (en) 2019-11-27 2021-06-03 Applied Materials, Inc. Processing chamber with multiple plasma units
KR20220108111A (ko) 2019-11-27 2022-08-02 어플라이드 머티어리얼스, 인코포레이티드 선택적 갭 충전을 위한 듀얼 플라즈마 사전-세정

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958819A (ja) * 1982-09-29 1984-04-04 Hitachi Ltd 薄膜形成方法
US4500408A (en) * 1983-07-19 1985-02-19 Varian Associates, Inc. Apparatus for and method of controlling sputter coating
JPH0697660B2 (ja) * 1985-03-23 1994-11-30 日本電信電話株式会社 薄膜形成方法
JPH0750688B2 (ja) * 1986-09-24 1995-05-31 日本電信電話株式会社 薄膜形成法
US4872947A (en) * 1986-12-19 1989-10-10 Applied Materials, Inc. CVD of silicon oxide using TEOS decomposition and in-situ planarization process
US5000113A (en) * 1986-12-19 1991-03-19 Applied Materials, Inc. Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process
US4885074A (en) * 1987-02-24 1989-12-05 International Business Machines Corporation Plasma reactor having segmented electrodes
US4887005A (en) * 1987-09-15 1989-12-12 Rough J Kirkwood H Multiple electrode plasma reactor power distribution system
US4851370A (en) * 1987-12-28 1989-07-25 American Telephone And Telegraph Company, At&T Bell Laboratories Fabricating a semiconductor device with low defect density oxide
US4877641A (en) * 1988-05-31 1989-10-31 Olin Corporation Process for plasma depositing silicon nitride and silicon dioxide films onto a substrate
JPH02216851A (ja) * 1989-02-16 1990-08-29 Mitsubishi Electric Corp 半導体集積回路装置の製造方法
US5429070A (en) * 1989-06-13 1995-07-04 Plasma & Materials Technologies, Inc. High density plasma deposition and etching apparatus
DE69032952T2 (de) * 1989-11-15 1999-09-30 Haruhisa Kinoshita Trocken-Behandlungsvorrichtung
JP2640174B2 (ja) * 1990-10-30 1997-08-13 三菱電機株式会社 半導体装置およびその製造方法
WO1992012535A1 (en) * 1991-01-08 1992-07-23 Fujitsu Limited Process for forming silicon oxide film
JP3670277B2 (ja) * 1991-05-17 2005-07-13 ラム リサーチ コーポレーション 低い固有応力および／または低い水素含有率をもつＳｉＯ▲Ｘ▼フィルムの堆積法
JP2699695B2 (ja) 1991-06-07 1998-01-19 日本電気株式会社 化学気相成長法
US5279669A (en) * 1991-12-13 1994-01-18 International Business Machines Corporation Plasma reactor for processing substrates comprising means for inducing electron cyclotron resonance (ECR) and ion cyclotron resonance (ICR) conditions
US5444207A (en) * 1992-03-26 1995-08-22 Kabushiki Kaisha Toshiba Plasma generating device and surface processing device and method for processing wafers in a uniform magnetic field
US5710486A (en) * 1995-05-08 1998-01-20 Applied Materials, Inc. Inductively and multi-capacitively coupled plasma reactor
US5597438A (en) * 1995-09-14 1997-01-28 Siemens Aktiengesellschaft Etch chamber having three independently controlled electrodes
US5772771A (en) * 1995-12-13 1998-06-30 Applied Materials, Inc. Deposition chamber for improved deposition thickness uniformity

Also Published As

Publication number Publication date
KR100277609B1 (ko) 2001-02-01
US7294205B1 (en) 2007-11-13
JPH1012608A (ja) 1998-01-16
US5976993A (en) 1999-11-02
JP3927642B2 (ja) 2007-06-13

Similar Documents

Publication Publication Date Title
KR970067690A (ko) 고밀도 플라즈마 막의 고유 스트레스를 감소하기 위한 방법 및 그 장치
KR100372385B1 (ko) 박막형성방법 및 박막형성장치
CN112135925B (zh) 成膜装置和成膜方法
JP2687966B2 (ja) 半導体装置の製造方法
US7183177B2 (en) Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement
JPH07183097A (ja) 半導体作製のための、プラズマと、プラズマ点火装置及び誘導結合装置を有するプロセス反応装置を用いたワ−クピ−スの処理方法
JPH098014A (ja) プラズマ成膜方法及びその装置
KR980012066A (ko) 플라즈마 처리장치
JP3706027B2 (ja) プラズマ処理方法
US5948485A (en) Plasma deposition method and an apparatus therefor
US3479269A (en) Method for sputter etching using a high frequency negative pulse train
KR100238573B1 (ko) 박막형성방법 및 장치
US20100062613A1 (en) Method of processing a substrate
KR100960791B1 (ko) 플라즈마 도핑 장치
JPH07297175A (ja) プラズマ処理方法及びプラズマ処理装置
JPH1027780A (ja) プラズマ処理方法
TW200307328A (en) Semiconductor device producing method and semiconductor producing device
KR980011764A (ko) 전면 고밀도 플라즈마 증착 제공 방법 및 그 장치
JPH03263827A (ja) デジタルエツチング装置
JP3599670B2 (ja) プラズマ処理方法および装置
KR100957457B1 (ko) 정전척 및 기판 사이의 잔여 전하 제거 장치와 그 제거방법
JPS6147645A (ja) 薄膜形成方法
JP3257241B2 (ja) プラズマｃｖｄ方法
JPS5980932A (ja) プラズマ処理装置
JPH1180947A (ja) イオン化スパッタ装置

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110929

Year of fee payment: 12

FPAY Annual fee payment

Payment date: 20120927

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee