KR970060857A - Composite sync signal output circuit for video mute - Google Patents

Composite sync signal output circuit for video mute Download PDF

Info

Publication number
KR970060857A
KR970060857A KR1019960002081A KR19960002081A KR970060857A KR 970060857 A KR970060857 A KR 970060857A KR 1019960002081 A KR1019960002081 A KR 1019960002081A KR 19960002081 A KR19960002081 A KR 19960002081A KR 970060857 A KR970060857 A KR 970060857A
Authority
KR
South Korea
Prior art keywords
signal
video
output
outputting
composite
Prior art date
Application number
KR1019960002081A
Other languages
Korean (ko)
Other versions
KR0170737B1 (en
Inventor
하진수
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960002081A priority Critical patent/KR0170737B1/en
Publication of KR970060857A publication Critical patent/KR970060857A/en
Application granted granted Critical
Publication of KR0170737B1 publication Critical patent/KR0170737B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/77—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase
    • H04N9/78—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase for separating the brightness signal or the chrominance signal from the colour television signal, e.g. using comb filter

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Television Signal Processing For Recording (AREA)
  • Synchronizing For Television (AREA)

Abstract

본 발명은 비디오 뮤트시에 복합 동기 신호 출력회로를 공개한다. 제1비디오 신호 및 휘도신호와 색차 신호가 분리된 제2비디오 신호를 입력하고, 입력한 신호들로부터 비디오 뮤트 구간동안 복합 동기 신호만을 출력하기 위한 그 회로는, 제1 및 제2비디오 신호의 휘도신호를 출력하고, 출력되는 휘도신호로부터 복합 동기 신호만을 검출하여 출력하는 신호처리수단과, 신호처리수단으로부터 출력되는 복합 동기 신호를 반전하고, 반전된 신호의 레벨을 소정레벨로 변화시켜 출력하는 복합 동기 신호 처리수단 및 신호처리수단에서 출력되는 휘도신호와 제2비디오 신호의 휘도신호를 입력하고, 입력한 휘도신호들을 제1제어신호에 응답하여 선택적으로 출력하고, 제1제어신호에 응답하여 선택된 신호와, 입력한 복합 동기 신호 처리수단의 출력을 제2제어신호에 응답하여 선택적으로 출력하는 신호 선택수단을 구비하고, 비디오 뮤트시, 제1제어신호에 의해 제2비디오신호의 휘도신호가 선택되며, 제1모드에서 제2제어신호에 의해 복합 동기 신호 처리수단의 출력이 선택되고, 제2모드에서 제1제어신호에 응답하여 선택된 신호가 제2제어신호에 의해 다시 선택되는 것을 특징으로 하고, 비디오 뮤트구간동안 복합 동기 신호만을 출력하기 위한 회로의 구성이 간단하여 부품수가 감소하고, 이에 의해 재료비가 절감되는 효과가 있다.The present invention discloses a composite synchronous signal output circuit at the time of video muting. The circuit for inputting a first video signal, a second video signal in which a luminance signal and a color difference signal are separated, and outputting only a composite synchronizing signal during a video mute interval from the input signals, Signal processing means for outputting a signal and for outputting only a composite synchronous signal from the output luminance signal and for outputting a composite synchronous signal which is output from the signal processing means and for outputting the inverted signal at a predetermined level, A second video signal, and a second video signal, and outputs the selected luminance signal in response to the first control signal, and outputs the selected luminance signal in response to the first control signal. Signal and a signal selecting means for selectively outputting the output of the inputted composite synchronizing signal processing means in response to the second control signal The luminance signal of the second video signal is selected by the first control signal when the video is muted and the output of the composite synchronizing signal processing means is selected by the second control signal in the first mode, The signal selected in response to the signal is again selected by the second control signal, and the circuit for outputting only the composite synchronous signal during the video mute interval is simple in construction, thereby reducing the number of components, .

Description

비디오 뮤트시에 복합 동기 신호 출력회로Composite sync signal output circuit for video mute

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제4도는 본 발명에 의한 비디오 뮤트시에 복합 동기 신호 출력회로의 블럭도이다.FIG. 4 is a block diagram of a composite synchronous signal output circuit at the time of video mute according to the present invention.

Claims (4)

제1비디오 신호 및 휘도 신호와 색차 신호가 분리된 제2비디오 신호를 입력하고, 입력한 신호들로부터 비디오 뮤트 구간동안 복합 동기 신호만을 출력하기 위한 비디오 뮤트시에 복합 동기 신호 출력회로에 있어서, 상기 제1 및 제2비디오 신호의 휘도신호를 출력하고, 상기 출력되는 휘도신호로부터 복합 동기 신호만을 검출하여 출력하는 신호처리수단:상기 신호처리수단으로부터 출력되는 상기 복합 동기 신호를 반전하고, 반전된 신호의 레벨을 소정레벨로 변화시켜 출력하는 복합 동기 신호 처리수단 및 상기신호처리수단에서 출력되는 휘도신호와 상기 제2비디오 신호의 휘도 신호를 입력하고, 입력한 휘도신호들을 제1제어신호에 응답하여 선택적으로 출력하고, 상기 제1제어신호에 응답하여 선택된 신호와, 입력한 상기 복합 동기 신호 처리수단의 출력을 제2제어신호에 응답하여 선택적으로 출력하는 신호 선택수단을 구비하고, 상기 비디오 뮤트시, 상기 제1제어신호에 의해 상기 제2비디오신호의 휘도신호가 선택되며, 제1모드에서 상기 제2제어신호에 의해 상기 복합 동기 신호 처리수단의 출력이 선택되고, 제2모드에서 상기 제1제어신호에 응답하여 선택된 신호가 제2제어신호에 의해 다시 선택되는 것을 특징으로 하는 비디오 뮤트시에 복합 동기 신호 출력회로.There is provided a composite synchronous signal output circuit for inputting a first video signal, a second video signal in which a luminance signal and a color difference signal are separated, and outputting only a composite synchronous signal during a video mute interval from the input signals, Signal processing means for outputting a luminance signal of the first and second video signals and detecting and outputting only a composite synchronous signal from the outputted luminance signal and inverting the composite synchronous signal outputted from the signal processing means, And a luminance signal output from the signal processing means and a luminance signal of the second video signal, and outputs the inputted luminance signals in response to the first control signal And outputs the selected signal in response to the first control signal and the inputted composite synchronizing signal processing means And a signal selection means for selectively outputting an output in response to a second control signal, wherein the luminance signal of the second video signal is selected by the first control signal when the video is muted, The output of the composite synchronizing signal processing means is selected by the second control signal and the signal selected in response to the first control signal in the second mode is selected again by the second control signal. Synchronous signal output circuit. 제1항에 있어서, 상기 복합 동기 신호 처리수단은 상기 신호처리수단으로부터 출력되는 복합 동기 신호를 반전하여 출력하는 인버터 및 상기 인버터의 출력 레벨을 상기 소정 레벨로 변환하여 출력하는 레벨 변환기를 구비하는 것을 특징으로 하는 비디오 뮤트시에 복합 동기 신호 출력회로.The synchronous signal processing apparatus according to claim 1, wherein the composite synchronous signal processing means includes an inverter for inverting and outputting a composite synchronous signal output from the signal processing means, and a level converter for converting the output level of the inverter to the predetermined level and outputting Characterized by a composite synchronous signal output circuit for video muting. 제1항에 있어서, 상기 신호 선택수단은 상기 제1제어신호와 상기 제2제어신호를 논리곱하여 출력하는 논리곱;상기 신호처리수단의 출력과 상기 제2비디오 신호의 휘도 신호를 입력하고, 상기 제1제어신호에 응답하여 선택적으로 출력하는 제1선택수단 및 상기 제1선택수단의 출력과 상기 복합 동기 신호 처리수단의 출력을 입력하고, 상기 논리곱의 출력에 응답하여 선택적으로 출력하는 제2선택수단을 구비하는 것을 특징으로 하는 비디오 뮤트시에 복합 동기 신호 출력회로.2. The video signal processing apparatus according to claim 1, wherein the signal selecting means comprises: a logical product multiplying the first control signal by the logical sum of the second control signal and outputting the logical product; inputting an output of the signal processing means and a luminance signal of the second video signal, A second selection means for selectively outputting in response to the first control signal and a second selection means for inputting an output of the first selection means and an output of the composite synchronization signal processing means, And a selection means for selecting the output of the composite synchronizing signal output circuit. 제3항에 있어서, 상기 제1선택 수단과 상기 제2선택 수단은 집적회로로 구현되는 것을 특징으로 하는 비디오 뮤트시에 복합 동기 신호 출력회로.The composite synchronous signal output circuit according to claim 3, wherein the first selection means and the second selection means are implemented as an integrated circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960002081A 1996-01-30 1996-01-30 Output circuit of composite synchronization signals in video mute KR0170737B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960002081A KR0170737B1 (en) 1996-01-30 1996-01-30 Output circuit of composite synchronization signals in video mute

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960002081A KR0170737B1 (en) 1996-01-30 1996-01-30 Output circuit of composite synchronization signals in video mute

Publications (2)

Publication Number Publication Date
KR970060857A true KR970060857A (en) 1997-08-12
KR0170737B1 KR0170737B1 (en) 1999-03-20

Family

ID=19450359

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960002081A KR0170737B1 (en) 1996-01-30 1996-01-30 Output circuit of composite synchronization signals in video mute

Country Status (1)

Country Link
KR (1) KR0170737B1 (en)

Also Published As

Publication number Publication date
KR0170737B1 (en) 1999-03-20

Similar Documents

Publication Publication Date Title
KR870005279A (en) Controller
KR970060857A (en) Composite sync signal output circuit for video mute
KR950010615A (en) Screen generator for wide TV receiver
KR970019445A (en) Image synthesizer and receiver
WO1996038981A3 (en) Caption moving
KR970068489A (en) Synchronization circuit of composite video equipment
KR950022965A (en) Character or title signal mixer circuit of video equipment
KR940008434A (en) Pip screen mute circuit and method without pip input
KR970031825A (en) Data field sync signal and ghost cancellation reference signal generator
KR940023245A (en) Clamp Level Automatic Control Circuit
KR970031815A (en) Input Polarity Control Circuit of Synchronization Signal
KR930003675A (en) Synchronization signal insertion method and circuit
KR970057171A (en) Screen processing method during OSD operation in no signal state of television receiver
KR970078434A (en) Synchronization signal generator of television receiver
KR930024478A (en) Digital Voice Mute Device
KR950022785A (en) Video signal converter
KR970019561A (en) Horizontal Synchronization Signal Synchronizer
KR970078560A (en) Versatile video display
KR920015938A (en) White Balance Inspection Circuit
KR930019051A (en) Image signal conversion circuit
KR910004001A (en) Synchronous Signal Separation Circuit
KR970078462A (en) Data and control signal transmission circuit
KR950024567A (en) Prevents screen distortion when switching to wide mode
KR900013789A (en) Color tv signal decoding circuit
KR890009175A (en) Horizontal Synchronization Detection Circuit

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050929

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee