KR970019445A - Image synthesizer and receiver - Google Patents

Image synthesizer and receiver Download PDF

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Publication number
KR970019445A
KR970019445A KR1019960040448A KR19960040448A KR970019445A KR 970019445 A KR970019445 A KR 970019445A KR 1019960040448 A KR1019960040448 A KR 1019960040448A KR 19960040448 A KR19960040448 A KR 19960040448A KR 970019445 A KR970019445 A KR 970019445A
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KR
South Korea
Prior art keywords
signal
synthesizing
converting
analog
digital
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KR1019960040448A
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Korean (ko)
Inventor
에쯔로 야마우찌
야스히데 모기
Original Assignee
이데이 노브유끼
소니 가부시끼가이샤
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Publication of KR970019445A publication Critical patent/KR970019445A/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/265—Mixing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Studio Circuits (AREA)
  • Image Processing (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

디지털화상신호와 아날로그화상신호의 화상합성을 용이하게 실현한다. 디지털그래픽스신호(GD0-7)와 디지털화상신호(MD0-7)를 합성할 수 있는 셀렉터(8)와, 2계통의 아날로그영상신호를 합성할 수 있는 믹싱회로(10)와, 디지털영상신호를 아날로그영상신호로 변환하는 연산회로(11) 및 화상을 합성하기 위한 제어신호(S1)를 연산회로(11)에서 생기는 연산지연시간에 상당하도록 지연시키는 지연회로(12)가 설치된 디지털비디오엔코더(9)에 의해 구성한다.Image synthesis of digital image signals and analog image signals can be easily realized. A selector 8 for synthesizing the digital graphics signals GD0-7 and MD0-7, a mixing circuit 10 for synthesizing two analog video signals, and a digital video signal. A digital video encoder 9 provided with a calculation circuit 11 for converting an analog video signal and a delay circuit 12 for delaying a control signal S1 for synthesizing an image to correspond to a calculation delay time generated by the calculation circuit 11. It consists of).

Description

화상합성장치 및 수신장치Image synthesizer and receiver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

도 1은 본 발명의 실시의 형태인 화상합성장치를 갖춘 수신장치의 블록도이다,1 is a block diagram of a receiving apparatus with an image synthesizing apparatus according to an embodiment of the present invention.

도 2는 아날로그 영상신호와 그래픽스신호를 합성하는 경우의 타이밍차트를 나타낸 도면이다,2 is a diagram illustrating a timing chart when synthesizing an analog video signal and a graphics signal.

도 3은 본 실시의 형태의 화상합성장치에서 합성된 영상신호의 표시예를 나타낸 도면이다,Fig. 3 is a diagram showing a display example of a video signal synthesized in the image synthesizing apparatus of this embodiment.

도 4는 본 실시의 형태인 화상합성장치에 설치되어 있는 디지털비디오엔코더의 구성을 나타낸 도면이다,Fig. 4 is a diagram showing the configuration of a digital video encoder provided in the image synthesizing apparatus according to the present embodiment.

도 5는 종래의 화상합성장치의 일예를 나타낸 블록도이다,5 is a block diagram showing an example of a conventional image synthesizing apparatus.

도 6은 종래의 화상합성장치에서 아날로그영상신호와 그래픽스신호를 합성하는 경우의 타이밍차트를 나타낸 도면이다,FIG. 6 is a diagram illustrating a timing chart in the case of combining an analog video signal and a graphics signal in a conventional image synthesizing apparatus.

도 7은 종래의 지연회로가 설치되어 있는 화상합성장치의 일예를 나타낸 블록도이다.7 is a block diagram showing an example of an image synthesizing apparatus provided with a conventional delay circuit.

Claims (6)

2계통의 디지털화상신호를 소정의 타이밍으로 바꾸어서 합성할 수 있는 디지털신호합성수단과, 상기 디지털신호합성수단의 출력을 연산처리하여 아날로그화상신호로 변환하는 변환수단과, 상기 변환수단에서 출력된 아날로그화상신호와, 외부에서 입력된 아날로그화상신호와를 선택하여 합성할 수 있는 아날로그신호합성수단을 갖추고, 상기 변환수단에는 디지털화상신호를 아날로그화상신호로 변환하기 위한 연산수단과, 상기 아날로그신호합성수단에 공급되는 제어신호를 상기 연산수단에서 생기는 연산지연시간에 상당하도록 지연시키는 지연수단과, 를 갖추고 있는 것을 특징으로 하는 화상합성장치.Digital signal synthesizing means capable of converting two systems of digital image signals at a predetermined timing, and synthesizing them; And an analog signal synthesizing means for selecting and synthesizing an image signal and an externally input analog image signal. And delay means for delaying the control signal supplied to the control signal to correspond to the operation delay time generated by the calculation means. 제 1항에 있어서, 상기 2계통의 디지털화상신호의 한편은 사용자 인터페이스에서 출력되는 그래픽스데이터로 되어 있는 것을 특징으로 하는 화상합성장치.The image synthesizing apparatus according to claim 1, wherein one of said two systems of digital image signals is graphics data output from a user interface. 제 1항에 있어서, 상기 지연수단은 1 또는 2이상 설치되어 있는 것을 특징으로 하는 화상합성장치.The image synthesizing apparatus according to claim 1, wherein one or more delay means are provided. 디지털화상신호 및 아날로그화상신호가 입력되는 수신장치에 있어서, 2계통의 디지털화상신호를 소정의 타이밍으로 바꾸어서 합성할 수 있는 디지털신호합성수단과, 상기 디지털신호합성수단의 출력을 연산처리하여 아날로그화상신호로 변환하는 변환수단과, 상기 변환수단에서 출력된 아날로그화상신호와, 외부에서 입력된 아날로그화상신호를 선택하여 합성할 수 있는 아날로그신호합성수단을 갖추고, 상기 변환수단에는 디지털화상신호를 아날로그화상신호로 변환하기 위한 연산수단과, 상기 아날로그신호합성수단에 공급되어 있는 제어신호를 상기 연산수단에서 생기는 연산지연시간에 상당하도록 지연시키는 지연수단과, 를 갖추고 있는 것을 특징으로 하는 수신장치.1. A receiving apparatus into which a digital image signal and an analog image signal are input, comprising: digital signal synthesizing means capable of converting two systems of digital image signals at a predetermined timing, and synthesizing the result; And converting means for converting into a signal, an analog image signal output from said converting means, and an analog signal synthesizing means for selecting and synthesizing an externally input analog image signal. The converting means includes a digital image signal as an analog image. And calculation means for converting the signal into a signal, delay means for delaying a control signal supplied to said analog signal synthesizing means to correspond to an operation delay time generated by said calculation means. 제 4항에 있어서, 상기 2계통의 디지털화상신호의 한편은 사용자인터페이스에서 출력되는 그래픽스데이터로 되어 있는 것을 특징으로 하는 수신장치.5. A receiving apparatus according to claim 4, wherein one of the two digital image signals is graphics data output from a user interface. 제 4항에 있어서, 상기 지연수단은 1 또는 2이상 설치되어 있는 것을 특징으로 하는 수신장치.5. A receiving apparatus according to claim 4, wherein said delay means is provided with one or two or more. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960040448A 1995-09-20 1996-09-17 Image synthesizer and receiver KR970019445A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7264628A JPH0990921A (en) 1995-09-20 1995-09-20 Image synthesizer and receiver
JP95-264628 1995-09-20

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KR970019445A true KR970019445A (en) 1997-04-30

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY127855A (en) * 1999-06-09 2006-12-29 Mediatek Inc Corp Integrated video processing system having multiple video sources and implementing picture-in-picture with on-screen display graphics
JP5108877B2 (en) * 2007-05-08 2012-12-26 パナソニック株式会社 Display device
JP2014126774A (en) * 2012-12-27 2014-07-07 Mitsubishi Electric Corp Image processor, image display device and image processing method

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