KR970024255A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR970024255A
KR970024255A KR1019950033873A KR19950033873A KR970024255A KR 970024255 A KR970024255 A KR 970024255A KR 1019950033873 A KR1019950033873 A KR 1019950033873A KR 19950033873 A KR19950033873 A KR 19950033873A KR 970024255 A KR970024255 A KR 970024255A
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KR
South Korea
Prior art keywords
oxide film
layer
wsi
semiconductor device
cap oxide
Prior art date
Application number
KR1019950033873A
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Korean (ko)
Inventor
정연국
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950033873A priority Critical patent/KR970024255A/en
Publication of KR970024255A publication Critical patent/KR970024255A/en

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Abstract

본 발명은 반도체 소자에 관한 것으로, 특히 캔 산화막을 얇게 증착함으로써 게이트 폴리 형성시 게이트 산화막위의 캡 산화막, 실리사이드층 및 폴리 실리콘층을 한꺼번에 식감할 수 있게 함으로써 게이트 폴리 형성공정이 단순화된 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. In particular, a thin film of can oxide is deposited to allow the cap oxide, silicide, and polysilicon layers on the gate oxide to be etched at the same time. It relates to a manufacturing method.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 2 도(a) - (c)는 본 발명의 게이트 폴리 형성방법을 나타낸 공정단면도.(A)-(c) are process cross-sectional views showing the gate poly forming method of the present invention.

Claims (2)

게이트 폴리상에 실리사이드층 및 캡 산화막을 갖는 반도체 소자에 있어서, 필드 산화막이 형성된 반도체 기판의 활성영역에 게이트 산화막을 성장시키는 공정; 상기 반도체 기판 전면에 폴리 실리콘 및 WSi2를 차례로 증착하는 공정; 캡 산화막을 상기 WSi2층 보다 얇게 증착하여 상기 폴리 실리콘층, WSi2층 및 캡 산화막의 전체 두께가 일정 두께 이하가 되도록 하는 공정; 및 상기 폴리 실리콘층, WSi2층 및 캡 산화막을 한꺼번에 식각하여 게이트 폴리를 형성하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.A semiconductor device having a silicide layer and a cap oxide film on a gate poly, comprising: growing a gate oxide film in an active region of a semiconductor substrate on which a field oxide film is formed; Sequentially depositing polysilicon and WSi 2 on the entire surface of the semiconductor substrate; Depositing a cap oxide film thinner than the WSi 2 layer so that the total thickness of the polysilicon layer, the WSi 2 layer, and the cap oxide film is equal to or less than a predetermined thickness; And forming a gate poly by etching the polysilicon layer, the WSi 2 layer, and the cap oxide film at a time. 제 1 항에 있어서, 상기의 증착된 게이트 캡용 산화막의 두께는 100 내지 200Å의 범위내인 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the deposited gate cap oxide film has a thickness in a range of 100 to 200 GPa. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950033873A 1995-10-04 1995-10-04 Manufacturing method of semiconductor device KR970024255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950033873A KR970024255A (en) 1995-10-04 1995-10-04 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950033873A KR970024255A (en) 1995-10-04 1995-10-04 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
KR970024255A true KR970024255A (en) 1997-05-30

Family

ID=66582588

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950033873A KR970024255A (en) 1995-10-04 1995-10-04 Manufacturing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR970024255A (en)

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