KR930001353A - Bimos manufacturing method - Google Patents

Bimos manufacturing method Download PDF

Info

Publication number
KR930001353A
KR930001353A KR1019910009641A KR910009641A KR930001353A KR 930001353 A KR930001353 A KR 930001353A KR 1019910009641 A KR1019910009641 A KR 1019910009641A KR 910009641 A KR910009641 A KR 910009641A KR 930001353 A KR930001353 A KR 930001353A
Authority
KR
South Korea
Prior art keywords
forming
polysilicon
bimos
manufacturing
etching
Prior art date
Application number
KR1019910009641A
Other languages
Korean (ko)
Other versions
KR100209765B1 (en
Inventor
정철희
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910009641A priority Critical patent/KR100209765B1/en
Publication of KR930001353A publication Critical patent/KR930001353A/en
Application granted granted Critical
Publication of KR100209765B1 publication Critical patent/KR100209765B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

내용 없음No content

Description

바이모스 제조방법Bimos manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 (a)-(f)는 본 발명의 실시예에 따른 공정단면도.1 (a)-(f) are cross-sectional views of a process according to an embodiment of the present invention.

Claims (1)

실리콘기판(1)상에 산화층(2)과 질화막(3)을 차례로 형성하고 상기 산화층(2)을 식각하여 액티브 영역을 형성하는 공정과, 액티브 영역에 폴리실리콘(4)을 도포하고, 트랜지스터 부분의 폴리실리콘(4)을 소정의 두께까지 식각하는 공정과, 식각된 부분의 폴리실리콘에 불순물(n+)을 이온 주입하여, 매몰층을 형성하고 활성화시켜 단결정화 시킨후 통상의 이온 공정에 의해 소자를 형성하는 공정을 차례로 실시하여서 이루어진 바이모스 제조방법.Forming an active layer by sequentially forming an oxide layer 2 and a nitride film 3 on the silicon substrate 1, and etching the oxide layer 2 to form an active region, applying polysilicon 4 to the active region, and Etching the polysilicon 4 to a predetermined thickness, and implanting impurities (n + ) into the polysilicon of the etched portion, forming a buried layer and activating it to single crystallization, followed by a conventional ion process. A bimos manufacturing method formed by sequentially performing the process of forming an element. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910009641A 1991-06-12 1991-06-12 Method of fabricating bi-mos KR100209765B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910009641A KR100209765B1 (en) 1991-06-12 1991-06-12 Method of fabricating bi-mos

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910009641A KR100209765B1 (en) 1991-06-12 1991-06-12 Method of fabricating bi-mos

Publications (2)

Publication Number Publication Date
KR930001353A true KR930001353A (en) 1993-01-16
KR100209765B1 KR100209765B1 (en) 1999-07-15

Family

ID=19315666

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910009641A KR100209765B1 (en) 1991-06-12 1991-06-12 Method of fabricating bi-mos

Country Status (1)

Country Link
KR (1) KR100209765B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6740595B2 (en) * 2002-04-12 2004-05-25 Infineon Technologies Ag Etch process for recessing polysilicon in trench structures

Also Published As

Publication number Publication date
KR100209765B1 (en) 1999-07-15

Similar Documents

Publication Publication Date Title
KR950010018A (en) A method for manufacturing a semiconductor device including a semiconductor body having a field insulating area formed by a groove filled with an insulating material
KR940002952A (en) Semiconductor device and manufacturing method thereof
KR930001353A (en) Bimos manufacturing method
KR940016887A (en) Method of forming fine gate electrode of semiconductor device
KR930003366A (en) Device Separation Method of Semiconductor Device
KR900002402A (en) Semiconductor manufacturing method with reduced toppertage due to field separation
KR970052785A (en) Semiconductor device manufacturing method
KR920010830A (en) Device isolation oxide film formation method
KR970054209A (en) Transistors and Mask ROM Manufacturing Method Using the Transistors
KR940001346A (en) Method of manufacturing semiconductor device separator
KR910017634A (en) Memory Cell Capacitor Manufacturing Method
KR970003479A (en) Ambush contact forming method of semiconductor device
KR890001170A (en) Method of manufacturing polyside structure of semiconductor device
KR910005306A (en) No-beak isolation process using CVD
KR930015043A (en) Capacitor manufacturing method with sensing characteristics
KR920010827A (en) Device isolation method of semiconductor device
KR910013510A (en) Method for manufacturing memory device by double trench process
KR910017684A (en) Memory Cell Capacitor Manufacturing Method
KR960015855A (en) SOI structure and its manufacturing method
KR960002696A (en) Method of manufacturing thin film transistor
KR920020636A (en) Manufacturing process of semiconductor device
KR960042929A (en) Semiconductor device including SOI structure and manufacturing method thereof
KR910013260A (en) DRAM manufacturing method
KR910005441A (en) Buried contact formation method using silicide
KR970053941A (en) Method for manufacturing charge storage electrode of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090406

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee