KR910013510A - Method for manufacturing memory device by double trench process - Google Patents

Method for manufacturing memory device by double trench process Download PDF

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Publication number
KR910013510A
KR910013510A KR1019890018834A KR890018834A KR910013510A KR 910013510 A KR910013510 A KR 910013510A KR 1019890018834 A KR1019890018834 A KR 1019890018834A KR 890018834 A KR890018834 A KR 890018834A KR 910013510 A KR910013510 A KR 910013510A
Authority
KR
South Korea
Prior art keywords
nitride film
insulating material
memory device
trench
trench process
Prior art date
Application number
KR1019890018834A
Other languages
Korean (ko)
Other versions
KR930000715B1 (en
Inventor
박완준
허윤종
곽덕영
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019890018834A priority Critical patent/KR930000715B1/en
Publication of KR910013510A publication Critical patent/KR910013510A/en
Application granted granted Critical
Publication of KR930000715B1 publication Critical patent/KR930000715B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.No content.

Description

이중 트랜치 공정에 의한 기억소자의 제조방법Method for manufacturing memory device by double trench process

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 이중 트랜치 공정에 의한 기억소자의 단면도.2 is a cross-sectional view of the memory device by the double trench process of the present invention.

Claims (2)

기판(1)에 다 결정 실리콘(2)과 n형 불순물 주입영역(3)(4)을 형성한 후 절연물질(5)을 증착하고 1차로 트랜치를 형성하여 질화막(6)을 디포지션하며 노광작업으로 트랜치 영역의 질화막(6)을 제거후 다시 2차로 트랜치를 형성하여 절연물질(7)을 증착한 후 남은 질화막(6)을 식각하므로 접촉창(8)을 형성하며 통상의 n형 다결정 실리콘(9)(11)과 유전체(10)를 증착하여서 됨을 특징으로 하는 이중 트랜치 공정에 의한 기억소자의 제조방법.After forming polycrystalline silicon (2) and n-type impurity implantation regions (3) and (4) on the substrate (1), the insulating material (5) is deposited, and a trench is formed first to deposit the nitride film (6) and expose it. After removing the nitride film 6 of the trench region by the operation, the second trench is formed again, and the remaining nitride film 6 is etched after the insulating material 7 is deposited, thereby forming a contact window 8 to form a conventional n-type polycrystalline silicon. (9) A method of manufacturing a memory device by a double trench process, characterized in that by depositing (11) and dielectric (10). 제1항에 있어서, 질화막(6)은 절연물질(5)과 그리고 절연물질(7)은 질화막(6)과 각각 식각을이나 식각용액이 다름을 특징으로 하는 이중 트랜치 공정에 의한 기억소자의 제조방법.The method of claim 1, wherein the nitride film 6 is formed of an insulating material 5 and the insulating material 7 is different from the nitride film 6 by etching or etching solution, respectively. Way. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890018834A 1989-12-18 1989-12-18 Method for fabricating semiconductor memory device KR930000715B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890018834A KR930000715B1 (en) 1989-12-18 1989-12-18 Method for fabricating semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890018834A KR930000715B1 (en) 1989-12-18 1989-12-18 Method for fabricating semiconductor memory device

Publications (2)

Publication Number Publication Date
KR910013510A true KR910013510A (en) 1991-08-08
KR930000715B1 KR930000715B1 (en) 1993-01-30

Family

ID=19293105

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890018834A KR930000715B1 (en) 1989-12-18 1989-12-18 Method for fabricating semiconductor memory device

Country Status (1)

Country Link
KR (1) KR930000715B1 (en)

Also Published As

Publication number Publication date
KR930000715B1 (en) 1993-01-30

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