KR900002402A - Semiconductor manufacturing method with reduced toppertage due to field separation - Google Patents

Semiconductor manufacturing method with reduced toppertage due to field separation Download PDF

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Publication number
KR900002402A
KR900002402A KR1019880009246A KR880009246A KR900002402A KR 900002402 A KR900002402 A KR 900002402A KR 1019880009246 A KR1019880009246 A KR 1019880009246A KR 880009246 A KR880009246 A KR 880009246A KR 900002402 A KR900002402 A KR 900002402A
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KR
South Korea
Prior art keywords
layer
toppertage
reduced
semiconductor manufacturing
field separation
Prior art date
Application number
KR1019880009246A
Other languages
Korean (ko)
Other versions
KR920004907B1 (en
Inventor
안경호
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019880009246A priority Critical patent/KR920004907B1/en
Publication of KR900002402A publication Critical patent/KR900002402A/en
Application granted granted Critical
Publication of KR920004907B1 publication Critical patent/KR920004907B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

내용 없음No content

Description

필드 분리형성에 따른 토퍼러지가 감소된 반도체의 제조방법Semiconductor manufacturing method with reduced toppertage due to field separation

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도의 (가)~(바)는 본 발명 반도체의 제조공정 수직 단면도.2A to 2B are vertical cross-sectional views of a semiconductor manufacturing process of the present invention.

Claims (1)

기판(1)상에 산화막층(2)을 형성한후 니트라이드(Nitride)로 액티브층(3)을 형성하고 필드층을 임플렌트(Implant)하며, 임플랜트를 한 필드층(4)을 산화한 후 니트라이드를 에칭한다. 다음, 산화막층을 모두 에칭하고 다시 산화막층(5)를 데포하며, P/R층(6)을 코팅후 에치백(Etch Back)법에 의해 P/R층(6) 및 산화막층(5)을 기판까지 에칭하여 실리콘을 제거하여 활성영역(a) 및 필드 분리영역(b)이 형성하고, 게이트(7)를 형성하여 제조됨을 특징으로 하는 필드 분리형성에 따른 토퍼러지가 감소된 반도체의 제조방법.After the oxide layer 2 is formed on the substrate 1, the active layer 3 is formed of nitride, the field layer is implanted, and the implanted field layer 4 is oxidized. The nitride is then etched. Next, all oxide layers are etched, and the oxide layer 5 is depoted again, and the P / R layer 6 and the oxide layer 5 are coated by an etch back method after coating the P / R layer 6. Is manufactured by etching silicon to a substrate to remove silicon to form active regions (a) and field isolation regions (b), and to form gates (7). Way. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880009246A 1988-07-22 1988-07-22 Semiconductor manufacturing method of reduced topology due to a formation of field separation KR920004907B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880009246A KR920004907B1 (en) 1988-07-22 1988-07-22 Semiconductor manufacturing method of reduced topology due to a formation of field separation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880009246A KR920004907B1 (en) 1988-07-22 1988-07-22 Semiconductor manufacturing method of reduced topology due to a formation of field separation

Publications (2)

Publication Number Publication Date
KR900002402A true KR900002402A (en) 1990-02-28
KR920004907B1 KR920004907B1 (en) 1992-06-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880009246A KR920004907B1 (en) 1988-07-22 1988-07-22 Semiconductor manufacturing method of reduced topology due to a formation of field separation

Country Status (1)

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KR (1) KR920004907B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100428349B1 (en) * 2001-06-15 2004-04-28 현대자동차주식회사 Ejecting device of bumper mold

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7198707B2 (en) 2002-12-13 2007-04-03 Korea Power Engineering Co. Inc. Apparatus for cathodic protection in an environment in which thin film corrosive fluids are formed and method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100428349B1 (en) * 2001-06-15 2004-04-28 현대자동차주식회사 Ejecting device of bumper mold

Also Published As

Publication number Publication date
KR920004907B1 (en) 1992-06-22

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