KR950021399A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR950021399A
KR950021399A KR1019930031873A KR930031873A KR950021399A KR 950021399 A KR950021399 A KR 950021399A KR 1019930031873 A KR1019930031873 A KR 1019930031873A KR 930031873 A KR930031873 A KR 930031873A KR 950021399 A KR950021399 A KR 950021399A
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KR
South Korea
Prior art keywords
nitride film
pattern
photoresist pattern
oxide film
etching
Prior art date
Application number
KR1019930031873A
Other languages
Korean (ko)
Other versions
KR0154140B1 (en
Inventor
정영석
권오성
김의식
홍흥기
구영모
김세정
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
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Priority to KR1019930031873A priority Critical patent/KR0154140B1/en
Publication of KR950021399A publication Critical patent/KR950021399A/en
Application granted granted Critical
Publication of KR0154140B1 publication Critical patent/KR0154140B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체 장치의 제조방법에 관한 것으로서, 일반적인 LOCOS 구조에서 질화막과 산화막을 식각한후, 반도체기판을 등방성식각하고 제2질화막패턴을 형성시킨 다음, 소자분리산화막을 성장시킴으로써, 버즈빅을 억제하고 활성영역의 축소를 방지하여 공정마진을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein after etching a nitride film and an oxide film in a general LOCOS structure, isotropically etching the semiconductor substrate, forming a second nitride film pattern, and growing a device isolation oxide film, thereby suppressing buzzvik Technology to improve process margin by preventing shrinkage of active area.

Description

반도체소자의 소자분리막 제조방법.A device isolation film manufacturing method for a semiconductor device.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 내지 제5도는 본 발명의 실시예로 반도체소자의 소자분리막 형성공정을 도시한 단면도이다.1 to 5 are cross-sectional views showing a device isolation film forming process of a semiconductor device in accordance with an embodiment of the present invention.

Claims (1)

실리콘기판 상부에 산화막 및 제1질화막을 증착하는 공정과, 상기 제1질화막 상부에 제1소자분리 마스크용 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로하여 제1질화막과 산화막을 식각하여 제1질화막패턴과 산화막패턴을 형성하는 공정과, 노출된 실리콘기판의 일정두께를 식각하고 감광막패턴을 제거하는 공정과, 전체구조 상부에 제2질화막을 증착한 후, 상기 소자분리 마스크용 감광막패턴보다 조금 더 큰 제2차소자분리 마스크용 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로하여 노출된 제2질화막을 식각하여 상기 제1질화막패턴을 덮는 제2질화막패턴을 형성하는 공정과, 산화공정으로 노출된 실리콘기판을 산화시켜 토플로지가 완화된 소자 분리산화막을 형성하는 공정을 포함하는 반도체소자의 소자분리막 제조방법.Depositing an oxide film and a first nitride film on the silicon substrate, forming a photoresist pattern for the first device isolation mask on the first nitride film, and etching the first nitride film and the oxide film using the photoresist pattern as a mask Forming a first nitride film pattern and an oxide film pattern, etching a predetermined thickness of the exposed silicon substrate and removing a photoresist pattern, depositing a second nitride film on the entire structure, and then depositing the photoresist pattern for the device isolation mask. Forming a photoresist pattern for the second element isolation mask that is slightly larger than that; and etching a second nitride film exposed using the photoresist pattern as a mask to form a second nitride film pattern covering the first nitride film pattern; Fabricating a device isolation film of a semiconductor device, comprising: oxidizing a silicon substrate exposed by an oxidation process to form a device isolation oxide film having a reduced topology Way. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930031873A 1993-12-31 1993-12-31 Manufacture of semiconductor device KR0154140B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930031873A KR0154140B1 (en) 1993-12-31 1993-12-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930031873A KR0154140B1 (en) 1993-12-31 1993-12-31 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
KR950021399A true KR950021399A (en) 1995-07-26
KR0154140B1 KR0154140B1 (en) 1998-12-01

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ID=19374797

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930031873A KR0154140B1 (en) 1993-12-31 1993-12-31 Manufacture of semiconductor device

Country Status (1)

Country Link
KR (1) KR0154140B1 (en)

Also Published As

Publication number Publication date
KR0154140B1 (en) 1998-12-01

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