KR960015855A - SOI structure and its manufacturing method - Google Patents

SOI structure and its manufacturing method Download PDF

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KR960015855A
KR960015855A KR1019940027965A KR19940027965A KR960015855A KR 960015855 A KR960015855 A KR 960015855A KR 1019940027965 A KR1019940027965 A KR 1019940027965A KR 19940027965 A KR19940027965 A KR 19940027965A KR 960015855 A KR960015855 A KR 960015855A
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South Korea
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single crystal
crystal silicon
silicon layer
substrate
insulating film
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KR1019940027965A
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Korean (ko)
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KR0157965B1 (en
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이창재
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문정환
금성일렉트론 주식회사
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Priority to KR1019940027965A priority Critical patent/KR0157965B1/en
Priority to JP7008863A priority patent/JPH08139181A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76262—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 에스오아이(SOI)구조와 그 제조방법에 관한 것으로, 단결정 실리콘기판의 활성영역상에 필연막의 패턴을 형성하고, 그 절연막상에 단결정 실리콘층의 활성영역을 형성하며, 필드산화막을 그 단결정 실리콘층과 단결정 실리콘기판의 필드영역에 형성한다. 따라서, 본 발명은 단결정 실리콘기판을 식각하는 공정을 사용하지 않으면서 소자가 형성된 단결정 실리콘층을 단결정 실리콘기판으로부터 격리시켜 그 단결정 실리콘기판의 식각에 따른 소자의 오염을 방지할 수 있을 뿐 아니라 에스오아이(SOl)구조의 제조공정을 통상적인 반도체 제조공정에 용이하게 적용할 수 있다.The present invention relates to an SOI structure and a method of manufacturing the same, wherein a pattern of an inevitable film is formed on an active region of a single crystal silicon substrate, an active region of a single crystal silicon layer is formed on the insulating film, and a field oxide film is formed. It is formed in the field region of the single crystal silicon layer and the single crystal silicon substrate. Therefore, the present invention can isolate the single crystal silicon layer on which the device is formed from the single crystal silicon substrate without using the process of etching the single crystal silicon substrate, thereby preventing contamination of the device due to the etching of the single crystal silicon substrate as well as The manufacturing process of the (SOl) structure can be easily applied to a conventional semiconductor manufacturing process.

Description

에스오아이(SO1)구조와 그 제조방법S1 structure and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 에스오아이구조를 나타낸 단면도,3 is a cross-sectional view showing an SOH structure according to the present invention,

제4도 (가)∼(마)는 본 발명에 의한 에스오아이구조의 제조방법을 나타낸 단면 공정도.4 (a) to (e) are cross-sectional process diagrams showing a method for manufacturing an SOH structure according to the present invention.

Claims (13)

기판의 활성영역상에 절연막과 단결정 실리콘층의 패턴이 순차적으로 적층되어 있고, 그 단결정 실리콘층의 필드영역상에 필드산화층이 형성되어 있어 상기 단결정 실리콘층의 패턴이 상기 기판으로부터 격리되는 에스오아이 (SOI) 구조.A pattern of an insulating film and a pattern of a single crystal silicon layer is sequentially stacked on an active region of a substrate, and a field oxide layer is formed on a field region of the single crystal silicon layer so that the pattern of the single crystal silicon layer is isolated from the substrate. SOI) structure. 제1항에 있어서, 상기 필드산화층은 상기 단결정 실리콘층과 상기 기판의 필드영역상에 형성되는 것을 특징으로 하는 에스오아이(SOI)구조.The SOI structure according to claim 1, wherein the field oxide layer is formed on the single crystal silicon layer and the field region of the substrate. 기판의 활성영역상에 제1절연막을 형성하는 공정과;단결정 실리콘층을 상기 기판과 상기 제1절연막상에 형성하는 공정과:상기 단결정 실리콘층의 활성영역상에 제2절연막을 형성하는 공정과;상기 단결정 실리콘층의 필드영역상에 필드 절연층을 형성하는 공정을 포함하는 에스오아이(SOI)구조의 제조방법.Forming a first insulating film on the active region of the substrate; forming a single crystal silicon layer on the substrate and the first insulating film; forming a second insulating film on the active region of the single crystal silicon layer; ; Forming a field insulating layer on the field region of the single crystal silicon layer. 제3항에 있어서, 상기 단결정 실리콘층을 형성하는 공정이 단결정 실리콘층을 상기 단결정 실리콘층과 상기 제1절연막상에 증착하는 공정과;증착된 상기 단결정 실리콘층을 열처리하여 단결정 실리콘층으로 재결정화시키는 공정으로 이루어지는 것을 특징으로 하는 에스오아이(SOI)구조의 제조방법.The method of claim 3, wherein the forming of the single crystal silicon layer comprises: depositing a single crystal silicon layer on the single crystal silicon layer and the first insulating layer; Method for producing a SOI (SOI) structure, characterized in that consisting of a step. 제4항에 있어서, 상기 단결정 실리콘층은 비정질 실리콘층으로 대치될 수 있는 것을 특징으로 하는 에스오아이(SOl)구조의 제조방법.The method of claim 4, wherein the single crystal silicon layer can be replaced with an amorphous silicon layer. 제3항에 있어서, 상기 제1절연막이 산화막으로 이루어지는 젓을 특징으로 하는 에스오아이(SOI)구조의 제조방법.4. The method of manufacturing a SOI structure according to claim 3, wherein the first insulating film is made of an oxide film. 제3항에 있어서, 상기 제1절연막이 질화막으로 이루어지는 것을 특징으로 하는 에스오아이(SOI)구조의 제조방법.The method of manufacturing a SOI structure according to claim 3, wherein the first insulating film is formed of a nitride film. 제3항에 있어서, 상기 필드 절연층이 상기 기판과 단결정 실리콘층의 필드영역상에 형성되는 것을 특징으로 하는 에스오아이(SOI)구조의 제조방법.4. The method of claim 3, wherein the field insulating layer is formed on the field region of the substrate and the single crystal silicon layer. 제3항에 있어서, 상기 제2절연막은 질화막과 산화막 및 레지스트중 어느 하나로 이루어져 있는 것을 특징으로 하는 에스오아이(SOI)구조의 제조방법.4. The method of claim 3, wherein the second insulating film is formed of any one of a nitride film, an oxide film, and a resist. 기판의 합성영역상에 제1절연막을 형성하는 공정과; 단결정 실리콘층을 상기 기판과 상기 제1절연막상에 형성하는 공정과; 상기 단결정 실리콘층상에 제2절연막을 증착하는 공정과; 상기 단결정 실리콘층을 열처리하여 단결정 실리콘층으로 재결정화시키는 공정과; 상기 단결정 실리곤층의 활성영역상에 상기 증착된 절연막을 형성하는 공정과; 상기 단결정 실리콘층의 필드영역상에 필드 절연층을 형성하는 공정을 포함하는 에스오아이(SOI)구조의 제조방법.Forming a first insulating film on the composite region of the substrate; Forming a single crystal silicon layer on said substrate and said first insulating film; Depositing a second insulating film on the single crystal silicon layer; Heat-treating the single crystal silicon layer to recrystallize the single crystal silicon layer; Forming the deposited insulating film on an active region of the single crystal silicon layer; And forming a field insulating layer on the field region of the single crystal silicon layer. 제10항에 있어서, 상기 필드 절연층이 상기 단결정 실리콘층과 상기 기판의 필드영역상에 형성되는 것을 특징으로 하는 에스오아이(SOI)구조의 제조방법.The method of claim 10, wherein the field insulating layer is formed on the single crystal silicon layer and the field region of the substrate. 기판의 활성영역상에 제1절연막으로 형성하는 공정과; 단결정 실리콘층을 상기 기판과 상기 제1절연막상에 형성하는 공정과; 상기 단결정 실리콘층의 활성영역상에 제2절연막을 형성하는 공정과; 상기 단결정 실리콘층의 필드영역을 게거하는 공정과; 상기 기판의 필드영역상에 필드 절연층을 형성하는 공정을 포함하는 에스오아이(SOI)구조의 제조방법.Forming a first insulating film on the active region of the substrate; Forming a single crystal silicon layer on said substrate and said first insulating film; Forming a second insulating film on an active region of the single crystal silicon layer; Removing a field region of the single crystal silicon layer; And forming a field insulating layer on the field region of the substrate. 제12항에 있어서, 상기 단결정 실리콘층의 필드영역을 제거하는 공정이 실시된 후 상기 기판의 필드영역이 식각되는 것을 특징으로 하는 에스오아이(SOI)구조의 제조방법.The method of claim 12, wherein the field region of the substrate is etched after the process of removing the field region of the single crystal silicon layer is performed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940027965A 1994-10-28 1994-10-28 Soi structure and fabricating method therefor KR0157965B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019940027965A KR0157965B1 (en) 1994-10-28 1994-10-28 Soi structure and fabricating method therefor
JP7008863A JPH08139181A (en) 1994-10-28 1995-01-24 Soi structure and its manufacture

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KR1019940027965A KR0157965B1 (en) 1994-10-28 1994-10-28 Soi structure and fabricating method therefor

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KR960015855A true KR960015855A (en) 1996-05-22
KR0157965B1 KR0157965B1 (en) 1999-02-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100566311B1 (en) * 1999-07-30 2006-03-30 주식회사 하이닉스반도체 Method for forming semiconductor device having CMOS transistor and method of it

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100566311B1 (en) * 1999-07-30 2006-03-30 주식회사 하이닉스반도체 Method for forming semiconductor device having CMOS transistor and method of it

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Publication number Publication date
JPH08139181A (en) 1996-05-31
KR0157965B1 (en) 1999-02-01

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