KR960026159A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR960026159A
KR960026159A KR1019940034124A KR19940034124A KR960026159A KR 960026159 A KR960026159 A KR 960026159A KR 1019940034124 A KR1019940034124 A KR 1019940034124A KR 19940034124 A KR19940034124 A KR 19940034124A KR 960026159 A KR960026159 A KR 960026159A
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KR
South Korea
Prior art keywords
layer
forming
imo
metal pattern
semiconductor device
Prior art date
Application number
KR1019940034124A
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Korean (ko)
Inventor
황준
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940034124A priority Critical patent/KR960026159A/en
Publication of KR960026159A publication Critical patent/KR960026159A/en

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Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로, 절연막의 상부에 형성된 금속 패턴간의 간격이 좁아질 경우, 금속 패턴의 상부에 형성되는 층에서 보이드가 형성되는 것을 방지하기 위해 금속 패턴 상부에 형성되는 층을 식각하는 보이드 발생부위의 입구를 크게 한 후, 공정을 진행함으로써 보이드 발생으로 인한 반도체 소자의 불랭발생을 방지시켜 수율을 향상시키는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and when the gap between the metal pattern formed on the upper portion of the insulating layer is narrowed, the layer formed on the metal pattern to prevent the formation of voids in the layer formed on the upper portion of the metal pattern The present invention relates to a method for manufacturing a semiconductor device in which the inlet of the void generation site for etching is increased, and then the process is performed to prevent uncooling of the semiconductor device due to void generation and to improve yield.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2C도는 본 발명에 따른 반도체 소자의 제조방법에 따른 공정단계를 도시한 단면도.2C is a cross-sectional view showing process steps in accordance with a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (3)

실리콘 기판상에 절연 산화막을 형성하는 단계와, 상기 절연 산화막 상부에 일정간격 이격된 금속 패턴을 형성하는 단계와, 전체 구조 상부에 제1내측 금속 산화막(IMO)을 증착하는 단계와, 상기 제1IMO층 상부에 에스오지(SOG)층을 형성하는 단계로 이루어지는 반도체 소자 제조방법에 있어서, 상기 제1IMO층과 SOG층을 상부에서 차례로 일정두께 에치백(Etch back)하여 평탄화 시키는 동시에 금속패턴과 금속패턴 사이에 도포된 제1IMO층의 요부를 완만하게 형성하는 단계와, 상기 제2SOG층 상부에 제2IMO층을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming an insulating oxide film on the silicon substrate, forming a metal pattern spaced apart from each other on the insulating oxide film, depositing a first inner metal oxide film (IMO) on the entire structure, and forming the first IMO In the semiconductor device manufacturing method comprising the step of forming a layer of SOG (SOG) on the upper layer, the first IMO layer and the SOG layer is sequentially etched back by a predetermined thickness from the top to planarize the metal pattern and the metal pattern Forming a major portion of the first IMO layer applied therebetween; and forming a second IMO layer on the second SOG layer. 제1항에 있어서, 에치백으로 상기 제1IMO층 두께의 1/2 정도를 식각하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein about half of the thickness of the first IMO layer is etched using an etch back. 제1항에 있어서, 상기 금속패턴은 높이가 0.7㎛~1.0㎛이고, 그 간격이 0.8㎛ 이하로 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the metal pattern has a height of 0.7 μm to 1.0 μm and an interval of 0.8 μm or less. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940034124A 1994-12-14 1994-12-14 Manufacturing method of semiconductor device KR960026159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940034124A KR960026159A (en) 1994-12-14 1994-12-14 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940034124A KR960026159A (en) 1994-12-14 1994-12-14 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
KR960026159A true KR960026159A (en) 1996-07-22

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Application Number Title Priority Date Filing Date
KR1019940034124A KR960026159A (en) 1994-12-14 1994-12-14 Manufacturing method of semiconductor device

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KR (1) KR960026159A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040024714A (en) * 2002-09-16 2004-03-22 아남반도체 주식회사 Method for manufacturing multi-layered inter metal dielectric layer of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040024714A (en) * 2002-09-16 2004-03-22 아남반도체 주식회사 Method for manufacturing multi-layered inter metal dielectric layer of semiconductor device

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