KR970003689A - Gate pattern formation method of semiconductor device - Google Patents

Gate pattern formation method of semiconductor device Download PDF

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Publication number
KR970003689A
KR970003689A KR1019950016459A KR19950016459A KR970003689A KR 970003689 A KR970003689 A KR 970003689A KR 1019950016459 A KR1019950016459 A KR 1019950016459A KR 19950016459 A KR19950016459 A KR 19950016459A KR 970003689 A KR970003689 A KR 970003689A
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KR
South Korea
Prior art keywords
gate
gate material
gate pattern
high temperature
semiconductor device
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Application number
KR1019950016459A
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Korean (ko)
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KR0170338B1 (en
Inventor
전영진
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김광호
삼성전자 주식회사
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Priority to KR1019950016459A priority Critical patent/KR0170338B1/en
Publication of KR970003689A publication Critical patent/KR970003689A/en
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Publication of KR0170338B1 publication Critical patent/KR0170338B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

신규한 반도체 장치의 게이트 패턴 형성방법이 개시되어 있다.A novel method of forming a gate pattern of a semiconductor device is disclosed.

필드산화막이 형성된 반도체 기판의 활성영역에 초박막의 게이트 산화막을 형성하고 상기 결과물 상에 게이트 물질을 전면 증착하고 상기 게이트 물질을 패터닝하기 위한 건식 식각시 실리콘의 피팅(Pitting) 현상을 방지를 위해 게이트 패턴 이외의 영역에 소정 두께의 게이트 물질을 잔류시키면서 타임에치(time each)방식으로 개이트 패턴을 형성한다. 상기 게이트 패턴 이외의 영역에 잔류된 게이트 물질을 고온산화시키는 공정으로 이루어진다. 본 발명에 의하면, 근본으로 게이트 산화막두께에 관계없이 실리콘 피팅 현상을 방지할 수 있다.A gate pattern is formed to form an ultra-thin gate oxide layer in an active region of a semiconductor substrate on which a field oxide layer is formed, and to prevent pitting of silicon during dry etching for depositing a gate material on the resultant material and patterning the gate material. The gate pattern is formed in a time etch method while leaving the gate material having a predetermined thickness in other regions. A high temperature oxidation of the gate material remaining in regions other than the gate pattern is performed. According to the present invention, the silicon fitting phenomenon can be prevented essentially regardless of the gate oxide film thickness.

Description

반도체 장치의 게이트 패턴 형성방법Gate pattern formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 내지 제3도는 본 발명의 실시예에 의한 게이트 패턴 형성방법을 순차적으로 도시한 공정 단면도이다.1 to 3 are cross-sectional views sequentially illustrating a method of forming a gate pattern according to an embodiment of the present invention.

Claims (3)

반도체 장치의 제조방법에 있어서, 필드산화막이 형성된 반도체 기판의 활성영역에 초박막의 게이트 산화막을 형성하는 공정; 상기 결과물 상에 게이트 물질을 전면 증착하는 공정; 상기 게이트 물질을 패터닝하기위한 건식식각시 실리콘의 피팅(Pitting) 현상을 방지를 위해 게이트 패턴 이외의 영역에 소정 두께의 게이트 물질을 잔류시키면서 타임에치(time etch)방식으로 게이트 패턴을 형성하는 공정; 및 상기 게이트 패턴 이외의 영역에 잔류된 게이트 물질을 고온산화시키는 공정으로 이루어진 것을 특징으로 하는 게이트 패턴 형성방법.A method of manufacturing a semiconductor device, comprising: forming an ultrathin gate oxide film in an active region of a semiconductor substrate on which a field oxide film is formed; Depositing a gate material on the resultant surface; Forming a gate pattern by a time etch method while leaving a gate material having a predetermined thickness in a region other than the gate pattern to prevent pitting of silicon during dry etching for patterning the gate material. ; And high temperature oxidizing a gate material remaining in a region other than the gate pattern. 제1항에 있어서, 상기 게이트 물질은 빠른 산화특성을 갖는 폴리실리콘으로 이루어진 것을 특징으로 하는 게이트 패턴 형성방법.The method of claim 1, wherein the gate material is made of polysilicon having fast oxidation characteristics. 제1항에 있어서, 상기 고온산화 공정은 상기 잔류된 게이트 물질 전체가 완전 산화될 수 있도록 약 900℃의 고온에서 O2산화분위기 속에서 수행되는 것을 특징으로 하는 게이트 패턴 형성방법.The method of claim 1, wherein the high temperature oxidation process is performed in an O 2 oxidizing atmosphere at a high temperature of about 900 ° C. so that the entire remaining gate material can be completely oxidized. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950016459A 1995-06-20 1995-06-20 Gate pattern forming method of semiconductor device KR0170338B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950016459A KR0170338B1 (en) 1995-06-20 1995-06-20 Gate pattern forming method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950016459A KR0170338B1 (en) 1995-06-20 1995-06-20 Gate pattern forming method of semiconductor device

Publications (2)

Publication Number Publication Date
KR970003689A true KR970003689A (en) 1997-01-28
KR0170338B1 KR0170338B1 (en) 1999-03-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950016459A KR0170338B1 (en) 1995-06-20 1995-06-20 Gate pattern forming method of semiconductor device

Country Status (1)

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Publication number Publication date
KR0170338B1 (en) 1999-03-30

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