KR970023421A - Sense Amplifier Power Supply Circuit of Semiconductor Memory - Google Patents

Sense Amplifier Power Supply Circuit of Semiconductor Memory Download PDF

Info

Publication number
KR970023421A
KR970023421A KR1019950038715A KR19950038715A KR970023421A KR 970023421 A KR970023421 A KR 970023421A KR 1019950038715 A KR1019950038715 A KR 1019950038715A KR 19950038715 A KR19950038715 A KR 19950038715A KR 970023421 A KR970023421 A KR 970023421A
Authority
KR
South Korea
Prior art keywords
sense amplifier
power supply
supply circuit
signal
amplifier power
Prior art date
Application number
KR1019950038715A
Other languages
Korean (ko)
Other versions
KR0179853B1 (en
Inventor
조진희
Original Assignee
문정환
Lg 반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, Lg 반도체 주식회사 filed Critical 문정환
Priority to KR1019950038715A priority Critical patent/KR0179853B1/en
Publication of KR970023421A publication Critical patent/KR970023421A/en
Application granted granted Critical
Publication of KR0179853B1 publication Critical patent/KR0179853B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)

Abstract

본 발명은 반도체 기억소자의 센스앰프 전원 공급회로에 관한 것으로, 종래에는 재저장 전압과 기준전압 사이의 전압차가 줄어들면 차동증폭기의 이득이 줄어들어 재저장 구동용 트랜지스터의 구동능력이 저하되고, 재저장 전압이 기준전압 레벨로 되는데 긴 시간이 소요되므로 메모리 셀에 저장된 정보를 센싱하는데 긴 시간이 소요되어 센싱속도 향상에 제약이 따르는 문제점이 있다. 따라서, 본 발명은 재저장 전압과 기준전압 사이의 전압차가 줄어들어도 재저장 구동용 트랜지스터의 구동능력을 크게 하여 센싱속도를 향상시킴과 아울러 메모리 셀에 저장된 정보를 센싱하는 시간을 단축할 수 있도록 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier power supply circuit of a semiconductor memory device. In the related art, when the voltage difference between the restoring voltage and the reference voltage is reduced, the gain of the differential amplifier is reduced, so that the driving capability of the restoring driving transistor is reduced and the restoring is performed. Since it takes a long time for the voltage to reach the reference voltage level, it takes a long time to sense the information stored in the memory cell, which is problematic in that the sensing speed is limited. Therefore, the present invention improves the sensing speed by increasing the driving capability of the restore driving transistor even when the voltage difference between the restore voltage and the reference voltage decreases, and shortens the time for sensing information stored in the memory cell. .

Description

반도체 기억소자의 센스앰프 전원 공급회로Sense Amplifier Power Supply Circuit of Semiconductor Memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명 반도체 기억소자의 센스앰프 전원 공급회로도.3 is a sense amplifier power supply circuit diagram of a semiconductor memory device of the present invention.

Claims (4)

인에이블신호(ENL)에 의해 초기값을 제어하는 초기값 제어수단의 출력에 따라 입력 신호를 차동 증폭하는 차동 증폭수단과, 상기 차동 증폭수단의 출력에 따라 재저장 전압을 조절하여 주는 재저장 구동용 트랜지스터와 인에이블신호에 따라 센싱전압을 조절하여 주는 센싱구동용 트랜지스터의 제어에 의해 셀에 저장된 정보를 센싱하는 센스앰프와, 인에이블신호를 입력받아 지연 및 조합하여 만든 신호를 이용하여 차동 증폭수단을 시간에 따라 차등적으로 제어하도록 하는 신호발생수단으로 구성된 것을 특징으로 하는 반도체 기억소자의 센스앰프 전원 공급회로.Differential amplifying means for differentially amplifying the input signal according to the output of the initial value control means for controlling the initial value by the enable signal (ENL), and a restoring drive for adjusting the restoring voltage according to the output of the differential amplifying means. Differential amplification using a sense amplifier for sensing information stored in a cell under the control of a sensing driving transistor that adjusts a sensing voltage according to an enable transistor and an enable signal, and a signal formed by receiving and delaying and combining an enable signal. A sense amplifier power supply circuit for a semiconductor memory device, characterized by comprising signal generating means for differentially controlling the means over time. 제1항에 있어서, 신호발생수단은 인에이블신호를 1차적으로 일정시간동안 지연시키는 제1지연수단과, 상기 제1지연수단의 출력을 다시 일정 시간 지연시키는 제2지연수단과, 상기 제1 및 제2지연수단의 출력신호를 입력받아 낸드 조합하는 낸드게이트와, 상기 낸드게이트의 출력신호를 반전시켜 출력하는 낫 게이트로 이루어진 것을 특징으로 하는 반도체 기억소자의 센스앰프 전원 공급회로.2. The apparatus of claim 1, wherein the signal generating means comprises: first delay means for delaying an enable signal primarily for a predetermined time, second delay means for delaying the output of the first delay means again for a predetermined time, and the first And a NAND gate that receives the output signal of the second delay means and NAND-combines, and a sick gate that inverts and outputs the output signal of the NAND gate. 제1항에 있어서, 차동 증폭수단의 시간에 따른 차등 제어는 소오스 커플 페어(Source Coupled Pair)의 비를 달리하여 제어하도록 한 것을 특징으로 하는 반도체 기억소자의 센스앰프 전원 공급회로.2. The sense amplifier power supply circuit as set forth in claim 1, wherein the differential control according to time of the differential amplifying means is controlled by varying a ratio of source coupled pairs. 제3항에 있어서, 소오스 커플 페어의 비를 시간에 따라 달리하는 것은 소오스 커플 페이용 트랜지스터를 추가로 설치하여 시간에 따라 스위칭 하도록 한 특징으로 하는 반도체 기억소자의 센스앰프 전원 공급회로.4. The sense amplifier power supply circuit for semiconductor memory devices according to claim 3, wherein the ratio of the source couple pairs is changed over time by additionally providing a source couple pay transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950038715A 1995-10-31 1995-10-31 Sense amplifier power generating circuit KR0179853B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950038715A KR0179853B1 (en) 1995-10-31 1995-10-31 Sense amplifier power generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950038715A KR0179853B1 (en) 1995-10-31 1995-10-31 Sense amplifier power generating circuit

Publications (2)

Publication Number Publication Date
KR970023421A true KR970023421A (en) 1997-05-30
KR0179853B1 KR0179853B1 (en) 1999-04-15

Family

ID=19432314

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950038715A KR0179853B1 (en) 1995-10-31 1995-10-31 Sense amplifier power generating circuit

Country Status (1)

Country Link
KR (1) KR0179853B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100418582B1 (en) * 1996-06-29 2004-05-07 주식회사 하이닉스반도체 Sense amplifiers
KR100762866B1 (en) * 2001-06-27 2007-10-08 주식회사 하이닉스반도체 Dual power supply circuit of sense amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100418582B1 (en) * 1996-06-29 2004-05-07 주식회사 하이닉스반도체 Sense amplifiers
KR100762866B1 (en) * 2001-06-27 2007-10-08 주식회사 하이닉스반도체 Dual power supply circuit of sense amplifier

Also Published As

Publication number Publication date
KR0179853B1 (en) 1999-04-15

Similar Documents

Publication Publication Date Title
US5493234A (en) Voltage down converter for semiconductor memory device
KR970071820A (en) Sense amplifier
KR940020579A (en) Semiconductor Memory Device
KR950007445A (en) Charge transfer device
KR960032900A (en) Input buffer circuit for semiconductor integrated circuit
KR970008180A (en) Sense Amplifier Control Circuit of Semiconductor Memory Device
KR970055264A (en) Differential amplifier
KR980005007A (en) Semiconductor device for data sensing
KR910010834A (en) Amplification circuit
KR960019304A (en) Sense Amplifier Circuit of Semiconductor Memory Device
JP3172430B2 (en) Current sensing amplifier circuit of semiconductor memory device
KR970051107A (en) Internal power supply
KR930020443A (en) Data Retention (DR) Mode Control Circuit
KR970023421A (en) Sense Amplifier Power Supply Circuit of Semiconductor Memory
KR950009727A (en) Semiconductor memory
KR970024172A (en) Semiconductor Integrated Circuits and Semiconductor Input Devices (SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INPUT CIRCUIT)
KR100364421B1 (en) Circuit for driving sense amplifier
KR950021980A (en) Bootstrap circuit
KR960035636A (en) Current-Amplified Sense Amplifiers
KR100422820B1 (en) Sense amplifier of semiconductor memory device
KR100223734B1 (en) Sense amplifier for mask rom
KR100422814B1 (en) Device for measuring power of semiconductor memory cells
KR970051105A (en) Voltage level control device by trimming electric fuse of semiconductor memory device
KR970053974A (en) Voltage generating circuits and semiconductor devices
KR970023354A (en) Internal voltage level compensation circuit

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19951031

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19951031

Comment text: Request for Examination of Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19980629

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19980930

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19981128

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19981127

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20011017

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20021018

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20031017

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20041018

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20051019

Start annual number: 8

End annual number: 8

FPAY Annual fee payment

Payment date: 20061026

Year of fee payment: 9

PR1001 Payment of annual fee

Payment date: 20061026

Start annual number: 9

End annual number: 9

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

Termination category: Default of registration fee

Termination date: 20081010