KR100422814B1 - Apparatus for measuring power of semiconductor memory cell - Google Patents

Abstract

PURPOSE: An apparatus for measuring power of a semiconductor memory cell is provided to supply the reference current proportional to the current of a memory cell by controlling a reference current controller including MOS transistors. CONSTITUTION: An apparatus for measuring power of a semiconductor memory cell includes a memory cell, a differential amplifier, a sensing main controller, a sensing sub-controller, a bias controller, and a read operation controller. The memory cell(10) is connected to bit lines. The differential amplifier(30) is used for sensing and amplifying a current difference of a reference cell. The sensing main controller(40) and the sensing sub-controller(60) are used for controlling a sensing point of the differential amplifier. The bias controller(50) is used for controlling the bias applied to the memory cell and the reference cell. The read operation controller(70) is used for controlling a read operation by turning on or off a transmission gate according to the first and the second control signal. The apparatus for measuring power of the semiconductor memory cell further includes a reference current controller(90) for controlling the intensity of the reference current according to the external bias signal and the second control signal.

Description

Device for measuring power of semiconductor memory cells

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for measuring power supply of a semiconductor memory cell, and more particularly, by measuring a current of a memory cell and determining a magnitude of threshold voltages of MOS transistors of the memory cell based on the measured current. It relates to a power measuring device.

In general, a power measuring device of a semiconductor memory cell senses and amplifies the current and the reference current of the memory cell, thereby measuring the current flowing through the MOS transistor of the memory cell, and using the measured current value, determines the threshold voltage of the MOS transistor of the memory cell. To judge.

A power measuring apparatus of a conventional semiconductor memory cell will be described with reference to FIG. 1.

Referring to FIG. 1, a conventional power measuring apparatus of a semiconductor memory cell senses a current difference between a memory cell 10 connected to a bit line BL and a reference cell 20 connected to an inverting bit line / BL. The main control unit 40 is connected to the differential amplifier 30 for amplification, the bit line BL and the inverting bit line / BL, and the sensing main controller 40 and the bit line for controlling the sensing points of the differential amplifier 30. A bias control unit 50 connected to BL and an inversion bit line / BL, for controlling a bias applied to the memory cell 10 and the reference cell 20 by an inversion sense enable signal / SE; , Connected to the inverting bit line / BL, by the sensing sub-control unit 60 for controlling the sensing point of the differential amplifier 30, and by the first and second control signals CS1 and CS2 applied from the outside. It is connected between the read operation control unit 70 and the reference cell 20 and the differential amplifier 30 to control the read operation, and the read operation A transmission gate TRG turned on / off by the output signal of the controller 70, and a buffering unit 80 for buffering the signal output from the differential amplifier 30 and outputting the same through the output terminal OUT. .

The sensing main controller 40 is coupled to the bit line BL to be connected to the first sensing control means 41 for controlling the sensing point of the differential amplifier 30 and to the inverting bit line / BL. The second sensing control means 42 for controlling the sensing point of 30.

The first sensing control means 41 comprises a PMOS transistor PM41 and a diode PMOS transistor PM42 having a gate connected to the ground in series between a power supply voltage and a bit line BL, and a power supply voltage and a bit line ( A gate connected in series with each other in series between BLs is composed of a PMOS transistor PM43 and a diode PMOS transistor PM44 connected to ground.

The second sensing control means 41 comprises a PMOS transistor PM45 and a diode PMOS transistor PM47 having a gate connected to the ground in series between a power supply voltage and an inversion bit line / BL, and a power supply voltage and an inversion. A PMOS transistor PM47 and a diode PMOS transistor PM48 having a gate connected to ground sequentially connected in series between the bit lines / BL are provided.

Referring to the operation of the general sensing main control unit having the above structure is as follows.

Since the operations of the first and second sensing control means 41 and 42 are the same, only the operation of the first sensing control means 41 will be described as an example.

The gates of the PMOS transistors PM41 and PM43 are connected to the ground and are always turned on. Accordingly, the power supply voltage applied through the PMOS transistors PM41 and PM43 respectively passes through the diode PMOS transistors PM42 and PM44. The signal is transferred to the differential amplifier 30 through the bit line BL to increase the sensing point of the differential amplifier 30. By this operation, the sensing point of the differential amplifier 30 is increased by the second sensing control means 42.

The bias control unit 50 is connected to the inversion bit line / BL and the first and second bias control means 51 and 52 for controlling the bias applied to the memory cell 10 connected to the bit line BL. Third and fourth bias control means 53, 54 for controlling the bias applied to the reference cell 20.

The first bias control unit 51 is applied with an inverted sense enable signal / SE to one input terminal, and a type force terminal is connected to a source gate NOR51 connected to the source of the NMOS transistor NM51, and the gate is a gate gate NOR51. And an NMOS transistor NM51 connected between the differential amplifier 30 and the memory cell 10.

The second bias control unit 52 is applied with an inverted sense enable signal / SE to one input terminal, and the type force terminal is connected to the NOR gate NOR52 connected to the bit line BL, and the gate is the output terminal of the NOR gate NOR51. And an NMOS transistor NM52 connected between the power supply voltage and the memory cell 10.

The third bias control unit 53 is applied with an inverted sense enable signal / SE to one input terminal, and a type force terminal is connected to a source gate NOR53 connected to the source of the NMOS transistor NM53, and the gate is a gate gate NOR53. NMOS transistor NM53 connected to the output terminal of the differential amplifier 30 and the reference cell 20 is provided.

The fourth bias control means 54 is applied to the inverted sense enable signal / SE at one input terminal, and the type force terminal is connected to the inverted bit line / BL and the gate NOR54, and the gate is the gate NOR54. It is composed of an NMOS transistor NM54 connected to the output terminal of and connected between the power supply voltage and the reference cell 20.

Referring to the operation of the general bias control having the above structure is as follows.

Since the operation procedures of the first to fourth bias control means 51 to 54 are the same, only the operation of the first bias control means 51 will be described as an example.

In the initial state in which the source of the NMOS transistor NM51 has a low value, when the inverted sense enable signal / SE of the low state is applied, the NOR gate NOR51 outputs a high signal to turn on the NMOS transistor NM51. To apply a bias to the memory cell 10.

Subsequently, when the source voltage of the NMOS transistor NM51 increases, the NOR gate NOR outputs a low signal to turn off the NMOS transistor NM51 to control the excessive bias to be applied to the memory cell 10.

By continuously repeating the above operation, the amount of bias applied to the memory cell 10 is adjusted.

The second bias control means 52 also applies a bias to the memory cell 10 by the same process as the operation of the first bias control channel 51. High only, when the bias is stabilized, the second bias control means 52 is stopped.

The third and fourth bias control means 53 and 54 also control the bias of the reference cell 20 by the same operation process as described above.

However, the third bias control means 53 continuously controls the bias of the reference cell 20, but the fourth bias control means 54 is stopped when the bias of the reference cell 20 is stabilized.

The sensing sub-control unit 60 includes an NMOS transistor NM61 and an NMOS transistor NM62 and a PMOS transistor PM61 to which a first control signal CS1 is applied to a gate connected in series between the inverting bit line / BL and ground. ) And an NMOS transistor (NM63), an output terminal of which is connected to the gate of the NMOS transistor (NM62), an inversion sense enable signal (/ SE) is applied to the gate, and a source voltage and a source of the PMOS transistor (PM62) A PMOS transistor PM62 connected therebetween and an inverted sense enable signal / SE are applied to the gate, and an NMOS transistor NM64 connected between the gate and the ground of the PMOS transistor PM61.

Referring to the operation of the general sensing sub-control unit having the above structure as follows.

When the inverted sense enable signal / SE in the low state and the second control signal CS2 in the high state are applied, the NMOS transistors NM61 and NM62 are turned on, so that the sensing sub-control unit 60 performs the inversion bit line (//). The sensing current of the differential amplifier 30 is controlled by applying a predetermined current of BL to ground to prevent excessive current from flowing through the inverting bit line / BL to the differential amplifier 30.

The read operation control unit 70 includes inverters IV71 and IV72 for inverting the first and second control signals CS1 and CS2, and output signals of the inverters IV71 and IV72 to one input terminal and a type force stage, respectively. The input NAND gate NAND71 and an inverter IV73 for inverting the output signal of the NAND gate NAND71 are formed.

The buffering unit 80 configures a plurality of inverters IV81, IV82, and IV83 sequentially connected between the output terminal and the output terminal OUT of the differential amplifier 30.

Referring to the operation of the power measurement apparatus of the conventional semiconductor memory cell having the above structure is as follows.

When the first and second control signals CS1 and CS2 in the low state are applied, the NAND gate NAND71 of the read operation control unit 70 applies the low signal to the P-type gate of the transmission gate TRG. The inverter IV73 of the operation controller 70 inverts the output signal of the NAND gate NAND71 and applies a high signal to the N-type gate of the transmission gate TRG to turn on the transmission gate TRG.

Subsequently, the differential amplifier 30 senses the current difference between the memory cell 10 connected to the bit line BL and the reference cell 20 connected to the inverting bit line / BL and outputs the output terminal through the buffering unit 80. Output as (OUT).

That is, when the current of the memory cell 10 is relatively large, the differential amplifier 30 outputs a high signal, and when the current of the memory cell 10 is relatively small, the differential amplifier 30 outputs a low signal. .

The threshold voltage of the MOS transistor in the memory cell 10 may be determined by the current difference between the memory cell 10 and the reference cell 20 output through the above process.

However, the power measuring apparatus of the conventional semiconductor memory cell as described above has a problem that it takes a lot of time by measuring the threshold voltage of the MOS transistors of the memory cell using the current of the reference cell.

Accordingly, the present invention is to solve the above problems, a semiconductor that can reduce the current measurement time of the memory cell by adjusting the magnitude of the reference current proportional to the current flowing in the memory cell using a minimum MOS transistor It is an object of the present invention to provide a power measuring device of a memory cell.

1 is a circuit diagram of a power supply measuring apparatus of a conventional semiconductor memory cell.

2 is a circuit diagram of a power measurement apparatus for a semiconductor memory cell according to an embodiment of the present invention.

3 is a graph illustrating a distribution of output currents of a power measurement apparatus of a semiconductor memory cell according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: memory cell 20: reference cell

30: differential amplifier 40: sensing main controller

50: bias control unit 60: sensing sub-control unit

70: read operation control unit 80: buffering unit

90: reference current controller

In order to achieve the above object, the present invention provides a differential amplifier which senses a current difference between a memory cell connected to a bit line and a reference cell connected to an inverted bit line, differentially amplifies and outputs it through a buffering unit, and controls a sensing point of the differential amplifier. A sensing main control unit and a sub-control unit, a bias control unit for controlling a bias applied to the memory cell and the reference cell by an inversion sense enable signal, and a first and second control signals applied from the outside. An apparatus for measuring power of a semiconductor memory cell comprising a read operation control unit for controlling a read operation by controlling on / off, the reference current being proportional to the current of the memory cell by a bias signal and a second control signal applied from the outside. And a reference current controller for arbitrarily controlling the size of.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2 and 3.

Referring to FIG. 2, the apparatus for measuring power of a semiconductor memory cell of the present invention, like FIG. 1, includes a memory cell 10, a reference cell 20, a differential amplifier 30, and a sensing main controller 40. And a bias control unit 50, a sensing sub control unit 60, a read operation control unit 70, a transmission gate TRG, and a buffering unit 80.

In addition, the apparatus for measuring power of the semiconductor memory cell of the present invention arbitrarily controls the magnitude of the reference current proportional to the current of the memory cell 10 by the bias signal BIS and the second control signal CS2 applied from the outside. It further comprises a reference current control unit 90 for.

The reference current controller 90 includes an NMOS transistor NM91 to which a second control signal CS2 is applied to a gate and an NMOS to which a bias signal BIS is applied to a gate, which is connected in series between the inverting bit line / BL and ground. It consists of a transistor NM92.

Referring to the operation of the power measurement device of the semiconductor memory cell of the present invention having the above structure is as follows.

When the first control signal CS1 in the low state and the second control signal CS2 in the high state are applied, the NAND gate NAND71 of the read operation control unit 70 transmits the high signal to the P-type gate of the transmission gate TRG. In addition, the inverter IV73 of the read operation controller 70 applies a low signal to the N-type gate of the transmission gate TRG to turn off the transmission gate TRG.

At this time, since the NMOS transistor NM91 of the reference current controller 90 is turned on, a bias signal BIS, which can be arbitrarily adjusted, is applied to the gate of the NMOS transistor NM91 of the reference current controller 90, thereby A reference current proportional to the current of (10) is applied.

Accordingly, the differential amplifier 30 senses and amplifies the current of the memory cell 10 and the magnitude of the reference current generated by the reference current controller 90. That is, a high signal is output when the current of the memory cell 10 is relatively large, and a low signal is output when the current of the memory cell 10 is relatively small.

For example, when a low current is output when a reference current of 40 μm A is applied and a high signal is output when a reference current of 45 μm A is applied, the magnitude of the current flowing through the memory cell 10 is It can be seen that it is between 40 and 45 μm A, and then the magnitude of the threshold voltage of the MOS transistor of the memory cell 10 can be determined based on the measured current.

3 is a graph illustrating a distribution of current values output from a differential amplifier when generating a wide range of reference currents using a reference current controller of a power measuring device according to an embodiment of the present invention.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

As described above, the apparatus for measuring power of a semiconductor memory cell of the present invention arbitrarily controls a reference current controller composed of MOS transistors to supply a wide range of reference currents proportional to the current of the memory cell, thereby providing a shorter time. It provides an effect that can measure the magnitude of the threshold voltage of the MOS transistors of the memory cell.

Claims (2)

A differential amplifier which senses a current difference between the memory cell connected to the bit line and the reference cell connected to the inverting bit line, differentially amplifies and outputs it through the buffering unit, a sensing main controller and a sub-control unit for controlling a sensing point of the differential amplifier; By controlling the on / off of the transmission gate by controlling the bias applied to the memory cell and the reference cell by the inverted sense enable signal and the first and second control signals applied from the outside, In the power measuring device of a semiconductor memory cell comprising a read operation control unit for controlling the operation, And a reference current controller for arbitrarily controlling a magnitude of a reference current proportional to the current of the memory cell by a bias signal applied from the outside and the second control signal. The method of claim 1, wherein the reference current control unit And a first NMOS transistor to which a second control signal is applied to a gate and a second NMOS transistor to which a bias signal is applied to a gate, which is connected in series between the inverted bit line and ground.

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