KR970019657A - HTV receiver unit - Google Patents

HTV receiver unit Download PDF

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Publication number
KR970019657A
KR970019657A KR1019950028980A KR19950028980A KR970019657A KR 970019657 A KR970019657 A KR 970019657A KR 1019950028980 A KR1019950028980 A KR 1019950028980A KR 19950028980 A KR19950028980 A KR 19950028980A KR 970019657 A KR970019657 A KR 970019657A
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KR
South Korea
Prior art keywords
gate
signal
fsync
data
output
Prior art date
Application number
KR1019950028980A
Other languages
Korean (ko)
Inventor
김명수
Original Assignee
구자홍
엘지전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자홍, 엘지전자 주식회사 filed Critical 구자홍
Priority to KR1019950028980A priority Critical patent/KR970019657A/en
Publication of KR970019657A publication Critical patent/KR970019657A/en

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Abstract

본 발명은 HDTV수신시스템에 관한 것으로, 특히 채널변환 또는 잡음에 의한 리셋의 오동작을 막을수 있는 데이터 정렬장치를 비터비 디코더(Vitervbi Decorder)에 부가하여 시스템의 신뢰성을 높인 HDTV수신장치에 관한 것이다.The present invention relates to an HDTV receiving system, and more particularly, to an HDTV receiving apparatus having a high reliability by adding a data aligning device to a Vitervbi Decorder that can prevent malfunctions of channel reset or reset by noise.

상기와 같은 본 발명은 HDTV 수신장치는 필드동기 신호(Fsync)와 데이터 세그먼트 동기신호(DSsync)를 논리 연산 출력하는 제1AND게이트와, 상기 제1AND게이트의 출력신호와 메인 동기신호를 논리연산 출력하는 제2AND게이트와, 상기 제2AND게이트의 출력 클럭신호에 동기되어 입력데이타를 비터비 복호하는 비터비 디코더와, 상기 제2AND게이트의 출력 클럭신호에 동기되어 상기 비터비 디코더의 데이터를 디인터리버 및 RS 디코더로 지연 출력하는 자연수단부와, 메인 동기신호에 맞추어 상기 비터비 디코더의 출력데이타로 필드동기 신호(Fsync)의 위치를 나타내는 Fsync 위치 신호를 발생하는 Fsync 위치신호 발생부를 포함하여 이루어진다.As described above, the HDTV receiver includes a first AND gate for performing a logic operation on the field sync signal (Fsync) and a data segment sync signal (DSsync), and a logic operation for outputting the output signal and the main sync signal of the first AND gate. A Viterbi decoder for Viterbi decoding input data in synchronization with a second AND gate, an output clock signal of the second AND gate, and a deinterleaver and RS for data of the Viterbi decoder in synchronization with an output clock signal of the second AND gate. And a natural means unit for delayed output to the decoder and an Fsync position signal generator for generating an Fsync position signal indicating the position of the field sync signal Fsync as output data of the Viterbi decoder in accordance with the main sync signal.

Description

에이치디티브이(HDTV) 수신장치HTV receiver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 HDTV 수신장치의 상위블럭도3 is a block diagram of the HDTV receiver of the present invention.

제4도는 본 발명의 비터비 디코더의 상세블럭도4 is a detailed block diagram of a Viterbi decoder of the present invention.

제5도는 본 발명의 비터비 디코더의 동작타이밍도5 is an operation timing diagram of the Viterbi decoder of the present invention.

Claims (1)

필드동기 신호(Fsync)와 데이터 세그먼트 동기신호(DSsync)를 논리 연산 출력하는 제1AND게이트와, 상기 제1AND게이트의 출력신호와 메인 동기신호를 논리연산 출력하는 제2AND게이트와, 상기 제2AND게이트의 출력 클럭신호에 동기되어 입력데이타를 비터비 보호하는 비터비 디코더와, 상기 제2AND게이트의 출력 클럭신호에 동기되어 상기 비터비 디코더의 데이터를 디인터리버 및 RS 디코더로 지연 출력하는 지연수단부와, 메인 동기신호에 맞추어 상기 비터비 디코더의 출력데이타로 필드동기 신호(Fsync)의 위치를 나타내는 Fsync 위치 신호를 발생하는 Fsync 위치신호 발생부를 포함하여 구성됨을 특징으로 하는 HDTV 수신장치A first AND gate for performing logic operation on the field synchronization signal Fsync and the data segment synchronization signal DSsync, a second AND gate for performing logic operation on the output signal and the main synchronization signal of the first AND gate, and the second AND gate. A Viterbi decoder for protecting input data in synchronization with an output clock signal, a delay means for delaying and outputting data of the Viterbi decoder to a deinterleaver and an RS decoder in synchronization with an output clock signal of the second AND gate; And an Fsync position signal generator for generating an Fsync position signal indicating the position of the field sync signal (Fsync) as the output data of the Viterbi decoder in accordance with the synchronization signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950028980A 1995-09-05 1995-09-05 HTV receiver unit KR970019657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950028980A KR970019657A (en) 1995-09-05 1995-09-05 HTV receiver unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950028980A KR970019657A (en) 1995-09-05 1995-09-05 HTV receiver unit

Publications (1)

Publication Number Publication Date
KR970019657A true KR970019657A (en) 1997-04-30

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ID=66597234

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950028980A KR970019657A (en) 1995-09-05 1995-09-05 HTV receiver unit

Country Status (1)

Country Link
KR (1) KR970019657A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000045145A (en) * 1998-12-30 2000-07-15 전주범 Vsb demodulator of digital television receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000045145A (en) * 1998-12-30 2000-07-15 전주범 Vsb demodulator of digital television receiver

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