KR970008503A - Semiconductor package structure - Google Patents

Semiconductor package structure Download PDF

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Publication number
KR970008503A
KR970008503A KR1019950019587A KR19950019587A KR970008503A KR 970008503 A KR970008503 A KR 970008503A KR 1019950019587 A KR1019950019587 A KR 1019950019587A KR 19950019587 A KR19950019587 A KR 19950019587A KR 970008503 A KR970008503 A KR 970008503A
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KR
South Korea
Prior art keywords
semiconductor chip
semiconductor
mounting plate
package structure
semiconductor package
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Application number
KR1019950019587A
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Korean (ko)
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KR100193228B1 (en
Inventor
신원선
Original Assignee
황인길
아남산업 주식회사
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Priority to KR1019950019587A priority Critical patent/KR100193228B1/en
Publication of KR970008503A publication Critical patent/KR970008503A/en
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Publication of KR100193228B1 publication Critical patent/KR100193228B1/en

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Abstract

본 발명은 반도체 패키지에 관한 것으로, 종래의 반도체 패키지 구조는 반도체 칩(3)이 반도체 칩 탑재판(1)상에 놓이게 되고, 반도체 칩(3)과 반도체 칩 탑재판(1) 사이에는 에폭시(2)가 사용되므로, 탑재판을 지지하는 타이바에 다운셋이 있는 경우에도 패키지 내에서 반도체 칩(3)의 상대적인 높이가 높게 설정되어 반도체 칩(3)과 리드(5) 사이에 와이어 본딩시 와이어 루프가 높아져서 패키지의 두께가 상대적으로 두꺼워지므로, 반도체 칩(3)에서 발생되는 열을 방출하지 못하게 되어 제품의 수명을 단축되는 등의 문제점이 있었던 바, 본 발명은 반도체 칩 탑재판(1)의 저면으로 접착테이프(6)에 의해 반도체 칩(3)을 부착하여 상기 반도체 칩(3)과 리드(5)를 연결하는 와이어 루프의 높이를 낮추므로서 반도체 패키지의 두께를 얇게 형성하여 반도체 칩(3)에서 발생되는 열을 반도체 칩(3)의 앞, 뒤면에서 보다 용이하게 방출시킴으로서 제품의 수명을 연장시킬 수 있는 등의 효과가 있는 반도체 패키지 구조.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package. In the conventional semiconductor package structure, a semiconductor chip (3) is placed on a semiconductor chip mounting plate (1), and an epoxy (between) semiconductor chip (3) and a semiconductor chip mounting plate (1) is used. 2) is used, even when there is a downset in the tie bar supporting the mounting plate, the relative height of the semiconductor chip 3 is set high in the package, so that the wire at the time of wire bonding between the semiconductor chip 3 and the lead 5 Since the thickness of the package becomes relatively thick due to a high loop, there is a problem that the heat generated from the semiconductor chip 3 cannot be released and the life of the product is shortened. By attaching the semiconductor chip 3 to the bottom by an adhesive tape 6, the height of the wire loop connecting the semiconductor chip 3 and the lead 5 is reduced, thereby forming a thin thickness of the semiconductor package. 3) in A semiconductor package structure having an effect of extending the life of a product by releasing heat generated more easily from the front and back surfaces of the semiconductor chip 3.

Description

반도체 패키지 구조Semiconductor package structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 반도체 패키지 구조도로서 반도체 칩 하부에 히트싱크가 부착된 단면도, 제3도는 본 발명의 반도체 패키지 구조도로서 패키지의 상·하부 몰드일부를 제거된 단면도, 제4도는 본 발명의 반도체 패키지 구조도로서 반도체 칩의 저면이 노출되도록 패키지의 상·하부 몰드 일부가 제거된 단면도.2 is a cross-sectional view of a semiconductor package structure according to an embodiment of the present invention in which a heat sink is attached to a lower portion of a semiconductor chip. FIG. 3 is a cross-sectional view of a semiconductor package structure of the present invention in which a part of upper and lower molds is removed. FIG. A cross-sectional view of a package structure diagram in which portions of upper and lower molds of a package are removed to expose a bottom surface of a semiconductor chip.

Claims (4)

반도체 칩을 부착하는 반도체 칩 탑재판과, 상기 반도체 칩 탑재판의 주연부에 위치하는 리드와, 상기 리드와 반도체 칩에 본딩되는 와이어로 구성된 반도체 패키지를 구성함에 있어서, 상기 리드와 반도체 칩에 본딩되는 와이어 루프의 높이가 낮게 형성되도록 반도체 칩 탑재판의 저면으로 접착테이프에 의해 반도체 칩을 부착함을 특징으로 하는 반도체 패키지 구조.In a semiconductor package comprising a semiconductor chip mounting plate to which a semiconductor chip is attached, a lead positioned at a periphery of the semiconductor chip mounting plate, and a wire bonded to the lead and the semiconductor chip, the semiconductor chip mounting plate is bonded to the lead and the semiconductor chip. A semiconductor package structure, characterized in that the semiconductor chip is attached to the bottom of the semiconductor chip mounting plate by the adhesive tape so that the height of the wire loop is low. 제1항에 있어서, 상기 반도체 칩의 저면에 접착테이프에 의해 히트싱크를 부착함을 특징으로 하는 반도체 패키지 구조.The semiconductor package structure according to claim 1, wherein a heat sink is attached to a bottom surface of the semiconductor chip by an adhesive tape. 제1항 내지 제2항에 있어서, 상기 히트싱의 저면이 외부로 노출된 것을 특징으로 하는 반도체 패키지 구조.The semiconductor package structure according to claim 1, wherein the bottom surface of the heat sink is exposed to the outside. 제1항에 있어서, 상기 반도체 칩의 저면이 외부로 노출된 것을 특징으로 하는 반도체 패키지 구조.The semiconductor package structure of claim 1, wherein a bottom surface of the semiconductor chip is exposed to the outside. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019587A 1995-07-05 1995-07-05 Semiconductor package structure KR100193228B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019587A KR100193228B1 (en) 1995-07-05 1995-07-05 Semiconductor package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950019587A KR100193228B1 (en) 1995-07-05 1995-07-05 Semiconductor package structure

Publications (2)

Publication Number Publication Date
KR970008503A true KR970008503A (en) 1997-02-24
KR100193228B1 KR100193228B1 (en) 1999-06-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950019587A KR100193228B1 (en) 1995-07-05 1995-07-05 Semiconductor package structure

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KR100193228B1 (en) 1999-06-15

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