KR970053758A - Structure of Semiconductor Package - Google Patents

Structure of Semiconductor Package Download PDF

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Publication number
KR970053758A
KR970053758A KR1019950065452A KR19950065452A KR970053758A KR 970053758 A KR970053758 A KR 970053758A KR 1019950065452 A KR1019950065452 A KR 1019950065452A KR 19950065452 A KR19950065452 A KR 19950065452A KR 970053758 A KR970053758 A KR 970053758A
Authority
KR
South Korea
Prior art keywords
leads
attached
plastic plate
semiconductor chip
semiconductor package
Prior art date
Application number
KR1019950065452A
Other languages
Korean (ko)
Other versions
KR100426499B1 (en
Inventor
김승모
Original Assignee
황인길
아남산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 황인길, 아남산업 주식회사 filed Critical 황인길
Priority to KR1019950065452A priority Critical patent/KR100426499B1/en
Publication of KR970053758A publication Critical patent/KR970053758A/en
Application granted granted Critical
Publication of KR100426499B1 publication Critical patent/KR100426499B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 반도체 패키지의 구조에 관한 것으로, 열방출이 용이하고, 트립공정이 필요없으며 패키지의 두께를 얇게 형성하면서도 고집적화 및 고성능화하여 성능을 향상시킨 반도체 패키지로서, 반도체칩과; 상기 반도체칩이 중앙부에 부착되며 그 외측부로는 다수의 리드가 부착되고, 외부로 노출된느 히트싱크과; 상기 다수의 리드 상부에 부착되며 중앙부에는 다수의 리드 선단부보다 외측으로 위치되는 공간부를 갖는 플라스틱판과; 상기 다수의 리드와 리드 사이를 채우면서 플라스틱판을 부착하는 접착제와; 상기 반도체칩 상의 칩패드와 다수의 리드에 전기적 신호를 전달하기 위하여 본딩된 와이어와; 상기 반도체칩과 와이어를 보호하기 위하여 플라스틱판의 공간부를 채우는 액체에폭시로 구성된 반도체 패키지의 구조이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor package, which is easy to dissipate heat, does not require a tripping process, and has a thin package, and has a high integration and high performance to improve performance. A heat sink in which the semiconductor chip is attached to a central portion and a plurality of leads are attached to an outer portion thereof and exposed to the outside; A plastic plate attached to an upper portion of the plurality of leads and having a space portion at a central portion thereof located outward from the plurality of lead tips; An adhesive for attaching a plastic plate while filling between the plurality of leads and leads; Wires bonded to transfer electrical signals to chip pads and a plurality of leads on the semiconductor chip; In order to protect the semiconductor chip and the wire is a structure of a semiconductor package consisting of a liquid epoxy to fill the space portion of the plastic plate.

Description

반도체 패키지의 구조Structure of Semiconductor Package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 반도체 패키지의 구조를 보인 단면도,2 is a cross-sectional view showing the structure of a semiconductor package according to the present invention;

제3도는 본 발명에 의한 요부 평면도.3 is a plan view of main parts according to the present invention.

Claims (3)

반도체칩과; 상기 반도체칩이 중앙부에 부착되며 그 외측부로는 다수의 리드가 부착되고, 외부로 노출되는 히트싱크과; 상기 다수의 리드 상부에 부착되며 중앙부에는 다수의 리드 선단부보다 외측으로 위치되는 공간부를 갖는 플라스틱판과; 상기 다수의 리드와 리드 사이를 채우면서 플라스틱판을 부착하는 접착제와; 상기 반도체칩 상의 칩패드와 다수의 리드에 전기적 신호를 전달하기 위하여 본딩된 와이어와; 상기 반도체칩과 와이어를 보호하기 위하여 플라스틱판의 공간부를 채우는 액체에폭시를 채워서 경화시켜서 된 것을 특징으로 하는 반도체 패키지의 구조.A semiconductor chip; A heat sink in which the semiconductor chip is attached to a central portion and a plurality of leads are attached to an outer portion thereof and exposed to the outside; A plastic plate attached to an upper portion of the plurality of leads and having a space portion at a central portion thereof located outward from the plurality of lead tips; An adhesive for attaching a plastic plate while filling between the plurality of leads and leads; Wires bonded to transfer electrical signals to chip pads and a plurality of leads on the semiconductor chip; The semiconductor package structure, characterized in that to harden by filling the liquid to fill the space portion of the plastic plate to protect the semiconductor chip and the wire. 제1항에 있어서, 상기 히트싱크의 외측으로 부착되는 다수의 리드는 접착테이프로 부착되는 것을 특징으로 하는 반도체 패키지의 구조.The structure of claim 1, wherein the plurality of leads attached to the outside of the heat sink are attached with an adhesive tape. 제1항에 있어서, 상기 플라스틱판은 PCB재질인 것을 특징으로하는 반도체 패키지의구조.The structure of claim 1, wherein the plastic plate is a PCB material. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065452A 1995-12-29 1995-12-29 Structure of semiconductor package KR100426499B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065452A KR100426499B1 (en) 1995-12-29 1995-12-29 Structure of semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065452A KR100426499B1 (en) 1995-12-29 1995-12-29 Structure of semiconductor package

Publications (2)

Publication Number Publication Date
KR970053758A true KR970053758A (en) 1997-07-31
KR100426499B1 KR100426499B1 (en) 2004-05-31

Family

ID=37329329

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950065452A KR100426499B1 (en) 1995-12-29 1995-12-29 Structure of semiconductor package

Country Status (1)

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KR (1) KR100426499B1 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0697359A (en) * 1992-09-14 1994-04-08 Hitachi Ltd Mounting structure for lsi chip

Also Published As

Publication number Publication date
KR100426499B1 (en) 2004-05-31

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