KR100426499B1 - Structure of semiconductor package - Google Patents

Structure of semiconductor package Download PDF

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Publication number
KR100426499B1
KR100426499B1 KR1019950065452A KR19950065452A KR100426499B1 KR 100426499 B1 KR100426499 B1 KR 100426499B1 KR 1019950065452 A KR1019950065452 A KR 1019950065452A KR 19950065452 A KR19950065452 A KR 19950065452A KR 100426499 B1 KR100426499 B1 KR 100426499B1
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South Korea
Prior art keywords
semiconductor chip
leads
heat sink
plastic plate
attached
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KR1019950065452A
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Korean (ko)
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KR970053758A (en
Inventor
김승모
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1019950065452A priority Critical patent/KR100426499B1/en
Publication of KR970053758A publication Critical patent/KR970053758A/en
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Publication of KR100426499B1 publication Critical patent/KR100426499B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A structure of a semiconductor package is provided to prevent a crack occurring in a trip process by eliminating the necessity of a dam bar for interconnecting leads, and to extend lifetime of a product by easily irradiating the heat generated from a semiconductor chip upward and downward through a heat sink and liquid epoxy. CONSTITUTION: A plate-type heat sink(4) has a predetermined breadth. A semiconductor chip(1) is attached to the lower center of the heat sink. A plurality of leads(2) extend to the outer circumference of the heat sink, attached to the lower part of the heat sink that is an outer circumference of the semiconductor chip by using adhesion tape. A plastic plate(3) is attached to the leads by filling adhesive between the leads. The semiconductor chip is positioned in the center of the plastic plate. The plastic plate has a uniform space part to expose a lead of a predetermined length. A plurality of wires(5) electrically connect the semiconductor chip with the plurality of leads. Epoxy(6) is filled and hardened in the space part of the plastic plate to protect the semiconductor chip and the wire from the environments.

Description

반도체 패키지의 구조Structure of Semiconductor Package

본 발명은 반도체 패키지의 구조에 관한 것으로, 더욱 상세하게는 열방출이 용이하고, 트림공정이 필요없으며 패키지의 두께를 얇게 형성하면서도 고집적화 및 고성능화하여 성능을 향상시킨 반도체 패키지의 구조에 관한 것이다.The present invention relates to a structure of a semiconductor package, and more particularly, to a structure of a semiconductor package that is easy to dissipate heat, does not need a trimming process, and has a high thickness and high performance while forming a thin package.

일반적으로 반도체 패키지의 구조는 제 1 도에 도시된 바와같이 반도체칩(1)의 주연부에 위치되도록 리드프레임의 리드(2)가 형성되어 있고, 상기 리드(2)와반도체칩(1)의 상면에 구비된 칩 패드와는 와이어(5)로 본딩되어 있으며, 그 외부로는 산화 및 부식을 방지하기 위하여 컴파운드(9)로 몰딩하여 반도체 패키지를 구성한다. 이때, 반도체칩(1)의 동작시 발생되는 열을 효율적으로 방출하기 위하여 몰딩공정시 반도체칩(1) 하부에 히트싱크(4)를 부착한다.In general, as shown in FIG. 1, a lead package 2 of a lead frame is formed so as to be positioned at a peripheral portion of the semiconductor chip 1, and the top surface of the lead 2 and the semiconductor chip 1 is illustrated in FIG. 1. The chip pad provided in the is bonded with a wire 5, and the semiconductor pad is molded into the compound 9 to prevent oxidation and corrosion. At this time, in order to efficiently discharge the heat generated during the operation of the semiconductor chip 1, the heat sink 4 is attached to the lower portion of the semiconductor chip 1 during the molding process.

그러나, 이와같이 반도체 패키지를 제조하는 공정중에는 리드(2)와 리드(2)를 연결하고 있는 댐바를 절단하는 트림공정이 있는데, 이러한 트림공정은 리드에 크랙을 발생시키는 요인이 되어 패키지의 불량을 일으키는 요인이 되었던 것이다.However, in the process of manufacturing a semiconductor package as described above, there is a trimming process for cutting the dam bar connecting the leads 2 and 2, which causes cracks in the leads and causes package defects. It was a factor.

따라서, 본 발명은 이와같은 문제점을 해결하기 위하여 발명된 것으로, 반도체 패키지의 제조공정에서 트림공정을 없애고, 외부로 노출되는 히트싱크에 직접 반도체칩과 리드를 부착함으로서 열방출을 향상시키며, 패키지의 두께를 최대한 얇게 형성하여 박형화 할수 있는 반도체 패키지의 구조를 제공함에 그 목적이 있다.Therefore, the present invention was invented to solve such a problem, and eliminates the trimming process in the manufacturing process of the semiconductor package, improves heat dissipation by attaching the semiconductor chip and lead directly to the heat sink exposed to the outside, The object of the present invention is to provide a structure of a semiconductor package that can be made thinner by making thickness as thin as possible.

이러한, 본 발명의 목적을 달성하기 위해서는 반도체칩과; 상기 반도체칩이 중앙부에 부착되며 그 외측부로는 다수의 리드가 부착되고, 외부로 노출되는 히트싱크와; 상기 다수의 리드 상부에 부착되며 중앙부에는 다수의 리드 선단부 보다 외측으로 위치되는 공간부를 갖는 플라스틱판과; 상기 다수의 리드와 리드 사이를 채우면서 플라스틱판을 부착하는 접착제와; 상기 반도체칩 상의 칩패드와 다수의 리드에 전기적 신호를 전달하기 위하여 본딩된 와이어와; 상기 반도체칩과 와이어를 보호하기 위하여 플라스틱판의 공간부를 채우는 에폭시로 구성된 것을 특징으로 하는 반도체 패키지의 구조에 의해 가능하다.In order to achieve the object of the present invention, such a semiconductor chip; A heat sink in which the semiconductor chip is attached to a central portion and a plurality of leads are attached to an outer portion thereof and exposed to the outside; A plastic plate attached to an upper portion of the plurality of leads and having a space portion at a central portion thereof located outward from the plurality of lead tips; An adhesive for attaching a plastic plate while filling between the plurality of leads and leads; Wires bonded to transfer electrical signals to chip pads and a plurality of leads on the semiconductor chip; It is possible by the structure of the semiconductor package, characterized in that composed of epoxy to fill the space portion of the plastic plate to protect the semiconductor chip and the wire.

이하, 본 발명의 실시예를 첨부도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

제 2 도는 본 발명에 의한 반도체 패키지의 구조를 보인 단면도로서, 외부로 노출되는 히트싱크(4)의 일측면 중앙에는 반도체칩(1)이 부착되어 있고, 상기 히트싱크(4)의 외측으로는 다수의 리드(2)가 부착되어 있다. 이때, 상기 다수의 리드(2)는 접착테이프(7)에 의해 부착되는 것이다.2 is a cross-sectional view showing the structure of a semiconductor package according to the present invention, in which a semiconductor chip 1 is attached to the center of one side of the heat sink 4 exposed to the outside, and the outside of the heat sink 4 A plurality of leads 2 are attached. In this case, the plurality of leads 2 are attached by the adhesive tape (7).

또한, 상기 다수의 리드(2) 상면에는 중앙에 공간부를 갖는 플라스틱판(3)이 접착제(2')에 의해 부착되는 것으로, 이때, 상기 접착제(2')는 제 4 도에 도시된 바와같이 리드(2)와 리드(2)사이의 공간부를 채우고, 밖으로 유출되지 않을 정도의 양을 사용한다. 또한, 상기 플라스틱판(3)의 재질은 PCB 재질을 사용하는 것이 바람직하다.In addition, a plastic plate 3 having a space in the center is attached to the upper surface of the plurality of leads 2 by an adhesive 2 ', wherein the adhesive 2' is shown in FIG. The amount of space between the lid 2 and the lid 2 is filled, and an amount that does not flow out is used. In addition, the material of the plastic plate 3, it is preferable to use a PCB material.

상기 플라스틱판(3)의 중앙부에 형성된 공간부(3')는 제 3 도에 도시된 바와같이 다수의 리드(2) 선단부 보다 외측으로 위치될수 있는 공간을 갖음으로서, 반도체칩(1) 상의 칩패드와 리드(2) 선단을 와이어(5)로 본딩할수 있는 것이다.The space portion 3 ′ formed at the center of the plastic plate 3 has a space that can be located outward of the leading ends of the plurality of leads 2 as shown in FIG. 3, thereby providing a chip on the semiconductor chip 1. The tip of the pad and lead 2 can be bonded with a wire 5.

이와같이 부착된 상태에서 반도체칩(1)과 와이어(5)를 보호하기 위하여 상기 플라스틱판(3)의 공간부(3')에 액체에폭시(6)를 채워서 경화시킴으로서 패키지를 구성하는 것이다. 이때, 상기 액체에폭시(6)는 열전도성이 양호한 것을 사용하여 반도체칩(1)의 회로 동작시 발생되는 열을 상기 히트싱크(4)와 액체에폭시(6)를 통해 외부로 방출함으로서 패키지의 성능을 향상 시킬 수 있는 것이다.In order to protect the semiconductor chip 1 and the wire 5 in the attached state as described above, the package is constituted by filling the liquid epoxy 6 in the space 3 'of the plastic plate 3 and curing it. At this time, the liquid epoxy 6 uses a good thermal conductivity to release heat generated during the circuit operation of the semiconductor chip 1 to the outside through the heat sink 4 and the liquid epoxy 6 to improve the performance of the package. To improve it.

이와같은 반도체 패키지는 리드(2)와 리드(2)를 연결하고 있는 댐바가 없음으로서 트림공정이 필요없는 것이다. 또한, 히트싱크(4)의 일측면에 반도체칩(1)을부착하고, 그 외부를 액체에폭시(6)로 채워서 경화시킴으로서 패키지의 두께를 현저히 줄일수 있는 것이다. 뿐만 아니라, 반도체칩(1)이 부착되는 히트싱크(4)의 전면이 외부로 노출되므로 열방출의 효과도 극대화되는 것이다.Such a semiconductor package does not require a trimming process because there is no dam bar connecting the leads 2 and 2. In addition, the thickness of the package can be significantly reduced by attaching the semiconductor chip 1 to one side of the heat sink 4 and filling the outside with the liquid epoxy 6 to cure it. In addition, since the front surface of the heat sink 4 to which the semiconductor chip 1 is attached is exposed to the outside, the effect of heat dissipation is also maximized.

이상의 설명에서와 같이 본 발명은 종래의 얇은 반도체 패키지의 두께를 보다 더 얇게 만들수 있어 박형으로 할수 있고, 리드와 리드를 연결하는 댐바가 없으므로 트림공정이 필요없어 트림시 발생되는 크랙을 방지할수 있어 패키지의 불량을 방지하고, 반도체 칩에서 발생되는 열을 히트싱크와 액체에폭시를 통해 상하부로 보다 용이하게 방출시킴으로서 제품의 수명을 연장시킬수 있는 등의 효과가 있다.As described above, the present invention can make the thickness of the conventional thin semiconductor package thinner and thinner, and there is no dam bar connecting the lead and the lead, so that no cracking process is required because the trim process is unnecessary, so that the package can be prevented. It is possible to prolong the life of the product by preventing the defects and by releasing heat generated from the semiconductor chip to the upper and lower parts more easily through the heat sink and the liquid epoxy.

제 1 도는 종래의 반도체 패키지의 구도를 보인 단면도1 is a cross-sectional view showing a structure of a conventional semiconductor package

제 2 도는 본 발명에 의한 반도체 패키지의 구조를 보인 단면도2 is a cross-sectional view showing the structure of a semiconductor package according to the present invention

제 3 도는 본 발명에 의한 요부 평면도3 is a plan view of main parts according to the present invention

제 4 도는 제 2 도의 A-A선 확대 단면도4 is an enlarged sectional view taken along the line A-A of FIG.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1 ; 반도체칩 2 ; 리드One ; Semiconductor chip 2; lead

3 ; 플라스틱판 4 ; 히트싱크3; Plastic plate 4; Heatsink

5 ; 와이어 6 ; 액체에폭시5; Wire 6; Liquid epoxy

Claims (2)

일정 넓이를 갖는 판상의 히트싱크와; 상기 히트싱크의 하부 중앙부에 접착된 반도체칩과; 상기 반도체칩의 외주연인 히트싱크의 하부에 접착테이프로 접착되어 상기 히트싱크의 외주연으로 연장된 다수의 리드와; 상기 다수의 리드와 리드 사이에 접착제가 충진되어 부착되며 중앙에는 상기 반도체칩이 위치하고, 일정 길이의 리드가 노출되도록 일정한 공간부를 갖는 플라스틱판과; 상기 반도체칩과 다수의 리드를 전기적으로 연결하는 다수의 와이어와; 상기 플라스틱판의 공간부에 충진 및 경화되어 상기 반도체칩과 와이어를 외부 환경으로부터 보호하는 에폭시를 포함하여 이루어진 것을 특징으로 하는 반도체패키지의 구조.A plate-shaped heat sink having a predetermined width; A semiconductor chip bonded to a lower center portion of the heat sink; A plurality of leads attached to a lower portion of the heat sink, which is the outer circumference of the semiconductor chip, by an adhesive tape and extending to the outer circumference of the heat sink; An adhesive is filled and attached between the plurality of leads and leads, and the semiconductor chip is positioned at the center thereof and has a predetermined space so that leads of a predetermined length are exposed; A plurality of wires electrically connecting the semiconductor chip and a plurality of leads; A semiconductor package structure comprising an epoxy filling and curing the space portion of the plastic plate to protect the semiconductor chip and the wire from the external environment. 제 1 항에 있어서, 상기 플라스틱판은 PCB재질인 것을 특징으로 하는 반도체 패키지의 구조.The structure of a semiconductor package according to claim 1, wherein the plastic plate is made of a PCB material.
KR1019950065452A 1995-12-29 1995-12-29 Structure of semiconductor package KR100426499B1 (en)

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KR100426499B1 true KR100426499B1 (en) 2004-05-31

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0697359A (en) * 1992-09-14 1994-04-08 Hitachi Ltd Mounting structure for lsi chip

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0697359A (en) * 1992-09-14 1994-04-08 Hitachi Ltd Mounting structure for lsi chip

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