KR970004026A - Removal Method of Polysilicon Stringer in Semiconductor Device Manufacturing - Google Patents

Removal Method of Polysilicon Stringer in Semiconductor Device Manufacturing Download PDF

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Publication number
KR970004026A
KR970004026A KR1019950019165A KR19950019165A KR970004026A KR 970004026 A KR970004026 A KR 970004026A KR 1019950019165 A KR1019950019165 A KR 1019950019165A KR 19950019165 A KR19950019165 A KR 19950019165A KR 970004026 A KR970004026 A KR 970004026A
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KR
South Korea
Prior art keywords
polysilicon
etch
stringer
spacer
polysilicon stringer
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Application number
KR1019950019165A
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Korean (ko)
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KR0147711B1 (en
Inventor
오진성
박찬동
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김주용
현대전자산업 주식회사
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Priority to KR1019950019165A priority Critical patent/KR0147711B1/en
Publication of KR970004026A publication Critical patent/KR970004026A/en
Application granted granted Critical
Publication of KR0147711B1 publication Critical patent/KR0147711B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 기판(1) 상에 폴리실리콘층(3, 5)을 포함하는 예정된 패턴(3 내지 6)을 형성할 때 생성되는 폴리실리콘스트링거(8)의 제거방법에 있어서, 기 형성된 상기 예정된 패턴의 측벽에 식각방지 스페이서(9′)를 형성하는 단계; 및 상기 식각방지 스페이서와의 식각 선택비를 이용하여 폴리실리콘 스트링거를 식각하는 단계를 포함하는 것을 특징으로 하며, 기 형성된 패턴을 손상시키지 않으면서 폴리실리콘 스트링거를 제거할 수 있어 소자의 제조수율 및 전기적 특성을 향상시킬 수 있도록 한 것이다.The present invention relates to a method for removing a polysilicon stringer (8) generated when forming a predetermined pattern (3 to 6) including a polysilicon layer (3, 5) on a semiconductor substrate (1). Forming an anti-etch spacer 9 'on the sidewall of the pattern; And etching the polysilicon stringer using an etch selectivity with the etch stop spacer, wherein the polysilicon stringer can be removed without damaging the previously formed pattern. It is to improve the characteristics.

Description

반도체 소자 제조시 폴리실리콘 스트링거의 제거방법Removal Method of Polysilicon Stringer in Semiconductor Device Manufacturing

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1E도는 본 발명에 따른 폴리실리콘 스트링거의 제거 과정도.1A to 1E are views illustrating a process for removing a polysilicon stringer according to the present invention.

Claims (6)

반도체 기판 상에 폴리실리콘층을 포함하는 예정된 패턴을 형성할 때 생성되는 폴리실리콘 스트링거의 제거방법에 있어서, 기 형성된 상기 예정된 패턴의 측벽에 식각방지 스페이서를 형성하는 단계; 및 상기 식각방지 스페이서와의 식각 선택비를 이용하여 폴리실리콘 스트링거를 식각하는 단계를 포함하는 것을 특징으로 하는 폴리실리콘 스트링거의 제거방법.A method of removing a polysilicon stringer produced when forming a predetermined pattern including a polysilicon layer on a semiconductor substrate, the method comprising: forming an anti-etch spacer on sidewalls of the predetermined pattern; And etching the polysilicon stringer by using an etching selectivity ratio with the etch stop spacer. 제1항에 있어서, 상기 기 형성된 예정된 패턴의 측벽에 식각방지 스페이서를 형성하는 단계는 전체구조 표면에 식각방지층을 형성하는 단계; 상기 폴리실리콘 스트링거가 노출되도록 전면식각을 수행하여 상기 예정된 패턴의 측벽에 식각방지층 스페이서를 형성하는 단계를 포함하는 것을 특징으로 하는 폴리실리콘 스트링거의 제거방법.The method of claim 1, wherein the forming of the anti-etch spacer on the sidewall of the predetermined pattern includes: forming an anti-etch layer on the surface of the entire structure; And etching the entire surface to expose the polysilicon stringer to form an etch stop layer spacer on the sidewall of the predetermined pattern. 제2항에 있어서, 상기 식각방지층은 질화층인 것을 특징으로 하는 폴리실리콘 스트링거의 제거방법.The method of claim 2, wherein the etch stop layer is a nitride layer. 제3항에 있어서, 상기 폴리실리콘 스트링거는 동방성 식각되는 것을 특징으로 하는 폴리실리콘 스트링거의 제거방법.4. The method of claim 3 wherein the polysilicon stringer is isotropically etched. 제4항에 있어서, 상기 폴리실리콘 스트링거는 SF6개스를 사용하여 제거되는 것을 특징으로 하는 폴리실리콘 스트링거의 제거방법.5. The method of claim 4, wherein said polysilicon stringer is removed using SF 6 gas. 제5항에 있어서, 상기 질화층 스페이서와 폴리실리콘 스트링거의 식각 선택비가 적어도 5:1 인 것을 특징으로 하는 폴리실리콘 스트링거의 제거방법.6. The method of claim 5, wherein the etch selectivity of the nitride layer spacer and the polysilicon stringer is at least 5: 1. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019165A 1995-06-30 1995-06-30 Method for removing poly-si stringer KR0147711B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950019165A KR0147711B1 (en) 1995-06-30 1995-06-30 Method for removing poly-si stringer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950019165A KR0147711B1 (en) 1995-06-30 1995-06-30 Method for removing poly-si stringer

Publications (2)

Publication Number Publication Date
KR970004026A true KR970004026A (en) 1997-01-29
KR0147711B1 KR0147711B1 (en) 1998-08-01

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KR0147711B1 (en) 1998-08-01

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