KR960035957A - Device Separation Method of Semiconductor Device - Google Patents
Device Separation Method of Semiconductor Device Download PDFInfo
- Publication number
- KR960035957A KR960035957A KR1019950004960A KR19950004960A KR960035957A KR 960035957 A KR960035957 A KR 960035957A KR 1019950004960 A KR1019950004960 A KR 1019950004960A KR 19950004960 A KR19950004960 A KR 19950004960A KR 960035957 A KR960035957 A KR 960035957A
- Authority
- KR
- South Korea
- Prior art keywords
- nitride film
- film
- nitride
- layer
- patterned
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 5
- 238000000926 separation method Methods 0.000 title 1
- 238000002955 isolation Methods 0.000 claims abstract description 3
- 150000004767 nitrides Chemical class 0.000 claims abstract 17
- 238000000034 method Methods 0.000 claims abstract 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract 7
- 238000005530 etching Methods 0.000 claims abstract 5
- 229920005591 polysilicon Polymers 0.000 claims abstract 3
- 125000006850 spacer group Chemical group 0.000 claims abstract 3
- 238000000206 photolithography Methods 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims abstract 2
- 238000000151 deposition Methods 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 1
- 210000003323 beak Anatomy 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- 230000035515 penetration Effects 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
신규한 반도체장치의 소자분리 방법이 개시되어 있다. 반도체기판 상에 제1 산화막 및 제1 질화막을 차례로 형성한 후, 사진식각 공정으로 상기 제1 질화막을 패터닝한다. 상기 패터닝된 제1 질화막을 마스크로 사용하여 상기 제1산화막을 식각한 후, 결과물 상에 얇은 제2 산화막 및 제2 질화막을 차례로 형성한다. 상기 제2 질화막이 형성된 결과물 상에 다결정실리콘을 증착하고, 이를 이방성 식각하여 상기 패터닝된 제1질화막의 측벽에 다결정실리콘 스페이서를 형성한다. 얇은 제2 질화막에 의해 제1 산화막의 측면으로 산소가 침투하는 것을 방지하여 버즈비크를 효과적으로 감소시킬 수 있다.A novel device isolation method for a semiconductor device is disclosed. After the first oxide film and the first nitride film are sequentially formed on the semiconductor substrate, the first nitride film is patterned by a photolithography process. After etching the first oxide layer using the patterned first nitride layer as a mask, a thin second oxide layer and a second nitride layer are sequentially formed on the resultant. Polycrystalline silicon is deposited on the resultant product on which the second nitride film is formed, and then anisotropically etched to form a polysilicon spacer on the sidewall of the patterned first nitride film. The penetration of oxygen into the side surface of the first oxide film by the thin second nitride film can effectively reduce the Burj beak.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2D도는 본 발명에 의한 반도체장치의 소자분리 방법을 설명하기 위한 단면도들.2D is a cross-sectional view illustrating a device isolation method of a semiconductor device according to the present invention.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950004960A KR0144911B1 (en) | 1995-03-10 | 1995-03-10 | Method of isolating the elements of the semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950004960A KR0144911B1 (en) | 1995-03-10 | 1995-03-10 | Method of isolating the elements of the semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960035957A true KR960035957A (en) | 1996-10-28 |
KR0144911B1 KR0144911B1 (en) | 1998-08-17 |
Family
ID=19409562
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950004960A KR0144911B1 (en) | 1995-03-10 | 1995-03-10 | Method of isolating the elements of the semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0144911B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100418300B1 (en) * | 1996-12-04 | 2004-04-17 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
-
1995
- 1995-03-10 KR KR1019950004960A patent/KR0144911B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0144911B1 (en) | 1998-08-17 |
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