KR0144911B1 - Method of isolating the elements of the semiconductor device - Google Patents
Method of isolating the elements of the semiconductor deviceInfo
- Publication number
- KR0144911B1 KR0144911B1 KR1019950004960A KR19950004960A KR0144911B1 KR 0144911 B1 KR0144911 B1 KR 0144911B1 KR 1019950004960 A KR1019950004960 A KR 1019950004960A KR 19950004960 A KR19950004960 A KR 19950004960A KR 0144911 B1 KR0144911 B1 KR 0144911B1
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- Prior art keywords
- nitride film
- nitride
- layer
- film
- patterned
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 125000006850 spacer group Chemical group 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000000206 photolithography Methods 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 abstract description 6
- 239000001301 oxygen Substances 0.000 abstract description 6
- 210000003323 beak Anatomy 0.000 abstract description 4
- 230000035515 penetration Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000007796 conventional method Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
신규한 반도체장치의 소자분리 방법이 개시되어 있다. 반도체기판상에 제1산화막 및 제1질화막을 차례로 형성한 후, 사진식각 공정으로 상기 제1질화막을 패터닝한다. 상기 패터닝된 제1질화막을 마스크로 사용하여 상기 제1산화막을 식각한 후, 결과물 상에 얇은 제2산화막 및 제2질화막을 차례로 형성한다. 상기 제2질화막이 형성된 결과물 상에 다결정실리콘을 증착하고, 이를 이방성 식각하여 상기 패터닝된 제1질화막의 측벽에 다결정실리콘 스페이서를 형성한다. 얇은 제2질화막에 의해 제1산화막의 측면으로 산소가 침투하는 것을 방지하여 버즈비크를 효과적으로 감소시킬 수 있다.A novel device isolation method for a semiconductor device is disclosed. After the first oxide film and the first nitride film are sequentially formed on the semiconductor substrate, the first nitride film is patterned by a photolithography process. After etching the first oxide layer using the patterned first nitride layer as a mask, a thin second oxide layer and a second nitride layer are sequentially formed on the resultant. Polycrystalline silicon is deposited on the resultant product on which the second nitride film is formed, and then anisotropically etched to form a polysilicon spacer on the sidewall of the patterned first nitride film. The penetration of oxygen into the side surface of the first oxide film by the thin second nitride film can effectively reduce the burj beak.
Description
제1도는 종래방법에 의한 반도체장치의 소자분리 방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a device isolation method of a semiconductor device by a conventional method.
제2a도 내지 제2d도는 본 발명에 의한 반도체장치의 소자분리 방법을 설명하기 위한 단면도들.2A to 2D are cross-sectional views illustrating a device isolation method of a semiconductor device according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10:실리콘기판 11:제1산화막10: silicon substrate 11: first oxide film
12:제1질화막 13:제2산화막12: first nitride film 13: second oxide film
14:제2질화막 15:다결정실리콘 스페이서14: second nitride film 15: polycrystalline silicon spacer
본 발명은 반도체장치의 소자분리 방법에 관한 것으로, 특히 다결정실리콘 스페이서를 사용하는 반도체장치의 소자분리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a device isolation method of a semiconductor device using a polycrystalline silicon spacer.
반도체 회로에서는 반도체기판 상에 형성된 트랜지스터, 다이오드 및 저항등의 여러 가지 소자들은 전기적으로 분리하는 것이 필요하다. 이러한 소자 분리 방법은, 통상적으로 실리콘의 부분산화법(LOCal Oxidation of Silicon; 이하 LOCOS 공정이라 한다)이 가장 많이 사용되고 있다.In a semiconductor circuit, various elements such as transistors, diodes, and resistors formed on a semiconductor substrate need to be electrically separated. In the device isolation method, a LOCal Oxidation of Silicon (LOCOS process) is most commonly used.
상기 LOCOS 공정은, 실리콘기판 상에 패드산화막 및 질화막을 차례로 형성하는 단계, 상기 질화막을 패터닝하는 단계, 및 실리콘기판을 선택적으로 산화시켜 소자분리막을 형성하는 단계로 이루어진다. 그러나, 상기 LOCOS 공정에 의하면, 실리콘기판의 선택산화시 마스크로 사용되는 질화막 하부에서 패드산화막의 측면으로 산소가 침투하면서 소자분리막의 끝부분에 버즈 비크(bird's beak)가 발생하게 된다. 이러한 버즈 비크에 의해 소자분리막이 버즈비크의 길이만큼 활성영역으로 확장되기 때문에 소자를 고밀도로 집적하기가 어렵다.The LOCOS process includes forming a pad oxide film and a nitride film sequentially on a silicon substrate, patterning the nitride film, and selectively oxidizing the silicon substrate to form an isolation layer. However, according to the LOCOS process, as the oxygen penetrates into the side of the pad oxide film under the nitride film used as the mask for the selective oxidation of the silicon substrate, a bird's beak is generated at the end of the device isolation film. Since the device isolation film extends into the active region by the length of the buzz beak by such a buzz beak, it is difficult to integrate the device at a high density.
이에 본 출원인은 다결정실리콘 스페이서를 이용하여 상기한 LOCOS 공정의 문제점을 해결할 수 있는 새로운 소자분리 방법을 발명하여 한국특허출원 제930591호로 출원하였으며, 이는 현재 한국특허청에 계속중이다.Accordingly, the present applicant has invented a new device isolation method that can solve the problems of the LOCOS process by using a polysilicon spacer, and filed it with Korean Patent Application No. 930391, which is currently being continued by the Korean Patent Office.
제1도는 상기 다결정실리콘 스페이서를 이용한 종래의 반도체장치의 소자분리 방법을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a device isolation method of a conventional semiconductor device using the polysilicon spacer.
제1도를 참조하면, 실리콘기판(1) 상에 패드산화막(2) 및 질화막(4)을 차례로 형성한 후, 사진식각 공정으로 상기 질화막(4) 및 패드산화막(2)을 패터닝한다. 이어서, 상기 결과물 상에 열산화 공정을 실시하여 얇은 산화막(6)을 형성한 후, 다결정실리콘을 결과물 저면에 증착한다. 다음에, 상기 다결정실리콘을 이방성 식각하여 패터닝된 질화막(4)의 측벽에 다결정실리콘 스페이서(8)를 형성한 후, 상기 질화막(4) 및 스페이서(8)를 산화마스크로 사용하여 실리콘기판(1)을 선택적으로 산화시킴으로서 소자분리막(도시되지 않음)을 형성한다.Referring to FIG. 1, after the pad oxide film 2 and the nitride film 4 are sequentially formed on the silicon substrate 1, the nitride film 4 and the pad oxide film 2 are patterned by a photolithography process. Subsequently, a thermal oxidation process is performed on the resultant to form a thin oxide film 6, and then polycrystalline silicon is deposited on the resultant bottom. Next, the polysilicon is anisotropically etched to form a polysilicon spacer 8 on the sidewall of the patterned nitride film 4, and then the silicon substrate 1 is formed using the nitride film 4 and the spacer 8 as an oxide mask. ) Is selectively oxidized to form an isolation layer (not shown).
그러나, 상기한 종래방법 역시 LOCOS 공정과 마찬가지로 패터닝된 질화막의 하부에서 패드산화막의 측면으로 산소가 침투하는 것을 효과적으로 억제하지 못한다.However, the conventional method, like the LOCOS process, does not effectively inhibit the penetration of oxygen from the lower side of the patterned nitride film to the side of the pad oxide film.
따라서, 본 발명의 목적은 상술한 종래방법의 문제점을 해결할 수 있는 반도체장치의 소자분리 방법을 제공하는데 있다.Accordingly, it is an object of the present invention to provide a device isolation method for a semiconductor device that can solve the problems of the conventional method described above.
상기 목적을 달성하기 위하여 본 발명은, 반도체기판 상에 제1산화막 및 제1질화막을 차례로 형성하는 단계; 사진식각 공정으로 상기 제1질화막을 패터닝하는 단계; 상기 패터닝된 제1질화막을 마스크로 사용하여 상기 제1산화막을 식각하는 단계; 상기 제1산화막이 식각된 결과물 상에 얇은 제2산화막 및 제2질화막을 차례로 형성하는 단계; 상기 제2질화막이 형성된 결과물 상에 다결정실리콘을 증착하고, 이를 이방성 식각하여 상기 패터닝된 제1질화막의 측벽에 다결정실리콘 스페이서를 형성하는 단계; 및 산화공정을 실시하여 소자분리막을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체장치의 소자분리 방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of sequentially forming a first oxide film and a first nitride film on a semiconductor substrate; Patterning the first nitride film by a photolithography process; Etching the first oxide layer using the patterned first nitride layer as a mask; Sequentially forming a thin second oxide film and a second nitride film on the resultant of etching the first oxide film; Depositing polycrystalline silicon on the resultant product on which the second nitride film is formed, and then anisotropically etching the same to form a polysilicon spacer on the sidewall of the patterned first nitride film; And forming a device isolation film by performing an oxidation process.
상기 제1산화막을 식각하는 단계에서, 상기 제1산화막을 습식식각 방법으로 언더커트(under cut)하여 상기 패터닝된 제1질화막의 하부에 공동을 형성할 수 있다. 이때, 상기 제2질화막은 상기 공동을 채우면서 형성하는 것이 바람직하다.In the etching of the first oxide layer, the first oxide layer may be under cut by a wet etching method to form a cavity in a lower portion of the patterned first nitride layer. In this case, the second nitride film is preferably formed while filling the cavity.
상기 다결정실리콘을 과도식각(over etch)하여 상기 제1질화막의 두께보다 낮게 상기 다결정실리콘 스페이서를 형설할 수 있으며, 제1산화막과 제1질화막의 사이에 다결정실리콘으로 이루어진 버퍼층을 더 형성할 수 있다.The polysilicon spacer may be overetched to form the polysilicon spacer lower than the thickness of the first nitride layer, and a buffer layer including polycrystalline silicon may be further formed between the first oxide layer and the first nitride layer. .
본 발명에 의하면, 얇은 제2질화막에 의해 패드용 제1산화막의 측면으로 산소가 침투하는 것을 방지함으로써 버즈비크를 효과적으로 감소시킬 수 있다.According to the present invention, it is possible to effectively reduce the buzz bequee by preventing oxygen from penetrating into the side surface of the first oxide film for pads by the thin second nitride film.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2d도는 본 발명에 의한 반도체장치의 소자분리 방법을 설명하기 위한 단면도들이다.2A to 2D are cross-sectional views illustrating a device isolation method of a semiconductor device according to the present invention.
제2a도는 제1산화막(11) 및 제1질화막(12)을 형성하는 단계를 도시한다. 실리콘기판(10) 상에 산화공정을 실시하여 스트레스 완화용 제1산화막(11)을 형성한 후, 예컨대 저압화학기상증착(LPCVD)방법으로 질화물을 증착하여 제1질화막(12)을 형성한다. 이어서, 사진식각 공정으로 상기 제1질화막(12)을 패터닝하여 소자분리막이 형성될 실리콘기판 부위를 개구한다.2A shows the steps of forming the first oxide film 11 and the first nitride film 12. After the oxidation process is performed on the silicon substrate 10 to form the first oxide film 11 for stress relaxation, nitride is deposited by, for example, low pressure chemical vapor deposition (LPCVD) to form the first nitride film 12. Subsequently, the first nitride layer 12 is patterned by a photolithography process to open the silicon substrate portion where the device isolation layer is to be formed.
제2b도는 상기 패터닝된 제1질화막(12)을 식각마스크로 사용하여 상기 제1산화막(11)을 식각하는 단계를 도시한다. 이때, 상기 제1산화막(11)을 습식식각 방법으로 언더커트함으로써 상기 패터닝된 제1질화막(12)의 하부에 공동(cavity)를 형성할 수 있다.FIG. 2B illustrates etching the first oxide layer 11 using the patterned first nitride layer 12 as an etching mask. In this case, a cavity may be formed under the patterned first nitride layer 12 by undercutting the first oxide layer 11 by a wet etching method.
제2c도는 제2산화막(13) 및 제2질화막(14)을 형성하는 단계를 도시한다. 상기 제1산화막(11)이 식각된 결과물 상에 산화공정을 실시하여 얇은 제2산화막(13)을 형성한 후, 상기 결과물 상에 질화물을 LPCVD 방법으로 얇게 증착하여 제2질화막(14)을 형성한다. 상기 패터닝된 제1질화막(12)의 하부에 공동을 형성한 경우는, 상기 공동을 채우도록 제2질화막(14)을 형성한다.2C shows the steps of forming the second oxide film 13 and the second nitride film 14. After the first oxide film 11 is etched to form a thin second oxide film 13 by an oxidation process, a thin nitride is deposited on the resultant by LPCVD to form a second nitride film 14. do. When a cavity is formed below the patterned first nitride film 12, a second nitride film 14 is formed to fill the cavity.
제2d도는 다결정실리콘 스페이서(15)를 형성하는 단계를 도시한다. 상기 얇은 제2질화막(14)이 형성된 결과물 상에 다결정실리콘을 증측한 후, 이를 이방성 식각하여 상기 패터닝된 제1질화막(12)의 측벽에 다결정실리콘 스페이서(15)를 형성한다. 이때, 상기 다결정실리콘을 과도식각하여 상기 패터닝된 제1질화막(12)의 두께보다 낮게 상기 다결정실리콘 스페이서(15)를 형성할 수 있다. 이어서, 상기 다결정실리콘 스페이서(15)가 형성된 결과물 상에 열산화 공정을 실시하여 개구된 실리콘기판 부위를 선택적으로 산화시킴으로써 소자분리막(도시되지 않음)을 형성한다. 이때, 상기 얇은 제2질화막(13)은 상기 열산화 공정시 버퍼층으로 작용하여 제1산화막(11)의 측면으로 산소가 침투하는 것을 막아주다가 결국에는 산화막으로 변화하게 된다.2d shows the step of forming the polysilicon spacer 15. After polycrystalline silicon is thickened on the resultant product on which the thin second nitride film 14 is formed, the polycrystalline silicon spacer 15 is formed on the sidewall of the patterned first nitride film 12 by anisotropic etching. In this case, the polysilicon may be over-etched to form the polysilicon spacer 15 lower than the thickness of the patterned first nitride layer 12. Subsequently, a thermal isolation process is performed on the resultant product on which the polysilicon spacers 15 are formed to selectively oxidize the open silicon substrate, thereby forming an isolation layer (not shown). At this time, the thin second nitride film 13 serves as a buffer layer in the thermal oxidation process to prevent oxygen from penetrating into the side surface of the first oxide film 11 and eventually changes to an oxide film.
본 발명의 바람직한 다른 실시예에 의하면, 상기 제1산화막과 제1질화막의 사이에 다결정실리콘으로 이루어진 버퍼층을 더 형성할 수 있다.According to another preferred embodiment of the present invention, a buffer layer made of polycrystalline silicon may be further formed between the first oxide film and the first nitride film.
따라서, 상술한 바와 같이 본 발명에 의한 반도체장치의 소자분리 방법에 의하면, 얇은 질화막에 의해 패드산화막의 측면으로 산소가 침투하는 것을 막아줌으로써 버즈비크를 효과적으로 감소시킬 수 있다.Therefore, according to the device isolation method of the semiconductor device according to the present invention as described above, it is possible to effectively reduce the Burj beak by preventing oxygen from penetrating the side of the pad oxide film by the thin nitride film.
본 발명이 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
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