KR970003834B1 - Manufacture for thin film transistor - Google Patents
Manufacture for thin film transistor Download PDFInfo
- Publication number
- KR970003834B1 KR970003834B1 KR93020630A KR930020630A KR970003834B1 KR 970003834 B1 KR970003834 B1 KR 970003834B1 KR 93020630 A KR93020630 A KR 93020630A KR 930020630 A KR930020630 A KR 930020630A KR 970003834 B1 KR970003834 B1 KR 970003834B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- thin film
- gate
- film transistor
- manufacture
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000010409 thin film Substances 0.000 title 1
- 239000010408 film Substances 0.000 abstract 2
- 239000012535 impurity Substances 0.000 abstract 2
- 238000000151 deposition Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 238000001953 recrystallisation Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to a method of making a bottom gate thin film transistor (TFT) that can increase on-current and ON/OFF ratio as well. This method includes the steps of forming a gate line on a semiconductor substrate and forming a gate insulating film; forming a side wall spacer doped with impurity ions on the gate/gate insulating film; depositing a body polysilicon all over the surface and performing recrystallization and thermal treatment to form an LDD by impurity diffusion; and performing high-density ion implantation with
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR93020630A KR970003834B1 (en) | 1993-10-06 | 1993-10-06 | Manufacture for thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR93020630A KR970003834B1 (en) | 1993-10-06 | 1993-10-06 | Manufacture for thin film transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950012645A KR950012645A (en) | 1995-05-16 |
KR970003834B1 true KR970003834B1 (en) | 1997-03-22 |
Family
ID=19365326
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR93020630A KR970003834B1 (en) | 1993-10-06 | 1993-10-06 | Manufacture for thin film transistor |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970003834B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1890322A3 (en) * | 2006-08-15 | 2012-02-15 | Kovio, Inc. | Printed dopant layers |
-
1993
- 1993-10-06 KR KR93020630A patent/KR970003834B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950012645A (en) | 1995-05-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20090223 Year of fee payment: 13 |
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LAPS | Lapse due to unpaid annual fee |