KR920013768A - Method for manufacturing transistor of thin film double gate structure - Google Patents

Method for manufacturing transistor of thin film double gate structure Download PDF

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Publication number
KR920013768A
KR920013768A KR1019900021634A KR900021634A KR920013768A KR 920013768 A KR920013768 A KR 920013768A KR 1019900021634 A KR1019900021634 A KR 1019900021634A KR 900021634 A KR900021634 A KR 900021634A KR 920013768 A KR920013768 A KR 920013768A
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KR
South Korea
Prior art keywords
gate
oxide film
film
polysilicon
forming
Prior art date
Application number
KR1019900021634A
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Korean (ko)
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KR940000988B1 (en
Inventor
이세경
장태식
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019900021634A priority Critical patent/KR940000988B1/en
Publication of KR920013768A publication Critical patent/KR920013768A/en
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Publication of KR940000988B1 publication Critical patent/KR940000988B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

내용 없음No content

Description

박막형 이중 게이트 구조의 트랜지스터 제조방법Method for manufacturing transistor of thin film double gate structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 제조 공정 단면도2 is a cross-sectional view of the manufacturing process of the present invention

Claims (2)

기판위에 메몰 산화막과 제1절연용 산화막을 차례로 형성한 후 상기 제1절연용 산화막위에 포토/에치 공정을 거쳐 제1게이트 폴리시리콘막 영역을 형성하는 단계, 상기 제1절연용 산화막의 제1게이트 폴리시리콘막 영역에 폴리시리콘을 증착하여 제1게이트 폴리시리콘막을 형성하는 단계, 제1게이트 산화막과 폴리시리콘층을 차례로 형성하고 이 폴리시리콘층의 설정된 영역에 이온을 주입하여 소오스/드레인을 형성하는 단계, 제2게이트 산화막과 제2게이트용 폴리시리콘막을 차례로 형성하고 이 제2게이트용 폴리시리콘막위에 포토/에치 공정을 실시하여 제2게이트 폴리 실리콘막을 형성하는 단계, 제2절연용 산화막을 형성하고 이 제2절연용 산화막에 포토/에치 공정을 거쳐 메탈 콘택트를 형성한 다음 이 메탈 콘택트내에 메탈을 증착하여 소오스/드레인 연결용 메탈 전극을 형성하는 단계가 차례로 포함됨을 특징으로 하는 박막형 이중 게이트 구조의 트랜지스터 제조방법.Forming a buried oxide film and a first insulating oxide film on the substrate in order, and then forming a first gate polysilicon film region on the first insulating oxide film through a photo / etch process; and a first gate of the first insulating oxide film. Depositing polysilicon in the polysilicon film region to form a first gate polysilicon film, sequentially forming a first gate oxide film and a polysilicon layer, and implanting ions into a predetermined region of the polysilicon layer to form a source / drain Forming a second gate polysilicon film by sequentially forming a second gate oxide film and a second gate polysilicon film, and performing a photo / etch process on the second gate polysilicon film to form a second insulating oxide film Then, a metal contact is formed on the second insulating oxide film through a photo / etch process, and then metal is deposited in the metal contact to form a source / de A method of producing a thin-film transistor with a double gate structure in which the connection feature is included in order to form a metal electrode. 제1항에 있어서,상기 소오스/드레인 및 채널 형성용 폴리시리콘층은 외부 불순물유입을 방지하기 위하여 큰 결정립 크기를 갖도록 형성함을 특징으로 하는 박막형 이중 게이트 구조의 트랜지스터 제조방법.The method of claim 1, wherein the source / drain and channel forming polysilicon layer is formed to have a large grain size in order to prevent external impurities from being introduced. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900021634A 1990-12-24 1990-12-24 Manufacturing method of double gate semiconductor device KR940000988B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900021634A KR940000988B1 (en) 1990-12-24 1990-12-24 Manufacturing method of double gate semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900021634A KR940000988B1 (en) 1990-12-24 1990-12-24 Manufacturing method of double gate semiconductor device

Publications (2)

Publication Number Publication Date
KR920013768A true KR920013768A (en) 1992-07-29
KR940000988B1 KR940000988B1 (en) 1994-02-07

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021634A KR940000988B1 (en) 1990-12-24 1990-12-24 Manufacturing method of double gate semiconductor device

Country Status (1)

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KR (1) KR940000988B1 (en)

Also Published As

Publication number Publication date
KR940000988B1 (en) 1994-02-07

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