KR940016892A - Method for manufacturing a polysilicon thin film transistor having a source-drain in which the impurity concentration varies linearly - Google Patents
Method for manufacturing a polysilicon thin film transistor having a source-drain in which the impurity concentration varies linearly Download PDFInfo
- Publication number
- KR940016892A KR940016892A KR1019920023516A KR920023516A KR940016892A KR 940016892 A KR940016892 A KR 940016892A KR 1019920023516 A KR1019920023516 A KR 1019920023516A KR 920023516 A KR920023516 A KR 920023516A KR 940016892 A KR940016892 A KR 940016892A
- Authority
- KR
- South Korea
- Prior art keywords
- drain
- source
- thin film
- film transistor
- polysilicon thin
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 title claims abstract 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract 7
- 229920005591 polysilicon Polymers 0.000 title claims abstract 7
- 239000010409 thin film Substances 0.000 title claims abstract 7
- 239000012535 impurity Substances 0.000 title claims abstract 5
- 239000010408 film Substances 0.000 claims abstract 6
- 239000004065 semiconductor Substances 0.000 claims abstract 5
- 238000005468 ion implantation Methods 0.000 claims abstract 3
- 239000002184 metal Substances 0.000 claims abstract 3
- 239000000758 substrate Substances 0.000 claims abstract 2
- 238000005530 etching Methods 0.000 claims 3
- 238000000151 deposition Methods 0.000 claims 2
- 238000004904 shortening Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 불순물 농도가 선형적으로 변하는 소오스-드레인을 갖는 폴리실리콘 박막 트랜지스터의 제조방법에 관한 것으로, 이온 주입과정을 단축하고 오프 전류를 감소시킬 수 있는 폴리실리콘 박막 트랜지스터의 제조방법을 제공함에 그 목적이 있다.The present invention relates to a method for manufacturing a polysilicon thin film transistor having a source-drain having a linearly varying impurity concentration, and provides a method for manufacturing a polysilicon thin film transistor capable of shortening an ion implantation process and reducing off current. There is a purpose.
본 발명은 상기 목적을 달성하기 위하여 반도체층(102)과 제 1 절연막(103)을 형성하는 제 1 공정, 상기 제 1 절연막(103)의 게이트 전극보다 큰 길이를 갖도록 하고 제 1 절연막(103)의 모서리가 선형적으로 경사지도록 한 제 2 공정, 도전층(105)을 증착하여 게이트 전극을 형성한 후 이온 주입으로 반도체(102)에 LDD층(107,108)과 오프 세트층(109)을 형성하는 제 3 공정, 제 2 절연막(110)을 증착한 후 접촉홀을 형성하여 소오스-드레인 금속층(111)을 형성하는 제 4 공정으로 구성됨을 특징으로 한다.The present invention provides a first process for forming the semiconductor layer 102 and the first insulating film 103, to have a length greater than the gate electrode of the first insulating film 103 in order to achieve the above object, and the first insulating film 103 In the second process in which the edges of the substrate are linearly inclined, the conductive layer 105 is deposited to form a gate electrode, and then the LDD layers 107 and 108 and the offset layer 109 are formed in the semiconductor 102 by ion implantation. And a fourth process of forming a source-drain metal layer 111 by forming a contact hole after the third process and the second insulating film 110 are deposited.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제 2 도는 본 발명의 제조방법을 나타내는 단면도.2 is a cross-sectional view showing a manufacturing method of the present invention.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920023516A KR950008262B1 (en) | 1992-12-07 | 1992-12-07 | Making method of polysilicon thin film transistor with source-drain having linear varied impurity concentration |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920023516A KR950008262B1 (en) | 1992-12-07 | 1992-12-07 | Making method of polysilicon thin film transistor with source-drain having linear varied impurity concentration |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940016892A true KR940016892A (en) | 1994-07-25 |
KR950008262B1 KR950008262B1 (en) | 1995-07-26 |
Family
ID=19344889
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920023516A KR950008262B1 (en) | 1992-12-07 | 1992-12-07 | Making method of polysilicon thin film transistor with source-drain having linear varied impurity concentration |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950008262B1 (en) |
-
1992
- 1992-12-07 KR KR1019920023516A patent/KR950008262B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950008262B1 (en) | 1995-07-26 |
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