KR970003984A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970003984A
KR970003984A KR1019950017497A KR19950017497A KR970003984A KR 970003984 A KR970003984 A KR 970003984A KR 1019950017497 A KR1019950017497 A KR 1019950017497A KR 19950017497 A KR19950017497 A KR 19950017497A KR 970003984 A KR970003984 A KR 970003984A
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KR
South Korea
Prior art keywords
etching
forming
bit line
semiconductor substrate
storage electrode
Prior art date
Application number
KR1019950017497A
Other languages
Korean (ko)
Inventor
전성도
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950017497A priority Critical patent/KR970003984A/en
Publication of KR970003984A publication Critical patent/KR970003984A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 비트라인과 저장 전극용 콘택홀을 각각 형성한 후에 불순물이 도프된 다결정실리콘막으로 이루어진 소오스와 드레인 전극을 형성하고, 열처리 공정으로 비트라인과 저장전극에 도프된 불순물을 노출된 반도체 기판으로 확산시켜 소오스와 드레인 영역의 LDD 구조를 형성하여 제조공정을 간단하게 하고, 뿐만 아니라 콘택홀 형성시 노출된 반도체 기판의 일정두께를 식각하여 콘택되는 면적을 증대시켜 콘택저항을 감소시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein source and drain electrodes made of a polysilicon film doped with impurities are formed after forming a bit line and a contact hole for a storage electrode. The doped impurities are diffused into the exposed semiconductor substrate to form LDD structures of the source and drain regions to simplify the manufacturing process, as well as to increase the contact area by etching a predetermined thickness of the exposed semiconductor substrate when forming contact holes. Technology to reduce contact resistance.

Description

반도체 소자의 제조 방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의하여 제조된 메모리 셀 트랜지스터를 도시한 단면도, 제2A도 내지 제2E도는 본 발명의 실시예에 따라 메모리 셀 트랜지스터를 형성하는 방법을 도시한 단면도.1 is a cross-sectional view showing a memory cell transistor fabricated according to the present invention, and FIGS. 2A to 2E are cross-sectional views showing a method of forming a memory cell transistor according to an embodiment of the present invention.

Claims (3)

제1도전형의 반도체 기판 일정 상부에 게이트 산화막과 게이트 전극을 형성하는 단계와, 게이트 전극의 측면에 제1절연막 스페이서를 형성하는 단계와, 전체 구조 상부에 제2절연막을 평탄하게 형성하는 단계와, 비트라인 콘택홀 마스크를 이용한 식각공정으로 제2절연막을 식각하고, 노출되는 실리콘 기판의 일정깊이까지 식각하고 상기 제2도전형 불순물이 도프된 다결정실리콘막을 증착하여 비트라인 콘택홀과 소오스를 각각 형성하는 단계와, 비트라인 마스크를 이용한 식각공정으로 상기 다결정실리콘막의 일정부분을 식각하여 비트라인을 형성하는 단계와, 전체 구조 상부에 제3절연막을 형성한 후, 저장전극 콘택홀 마스크를 이용한 식각공정으로 상기 제3절연막, 제2절연막을 식각하고, 노출되는 반도체 기판을 일정깊이 식각하고 저장전극 콘택홀과 드레인을 각각 형성하는 단계와, 전체 구조 상부에 제2도전형 불순물이 도프된 다결정실리콘막을 도포하여 저장 전극 마스크를 이용한 식각공정으로 다결정실리콘의 일정부분을 식각하여 저장전극을 형성하는 단계와, 열처리 공정으로 상기 비트라인과 저장전극에 도프된 불순물을 노출된 반도체 기판에 확산하여 소오스 및 드레인의 LDD 구조를 각각 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.Forming a gate oxide film and a gate electrode on a predetermined upper portion of the first conductive semiconductor substrate, forming a first insulating film spacer on a side surface of the gate electrode, and forming a second insulating film on the entire structure of the semiconductor substrate; And etching the second insulating layer by an etching process using a bit line contact hole mask, etching to a predetermined depth of the exposed silicon substrate, and depositing a polysilicon film doped with the second conductive impurity to form a bit line contact hole and a source, respectively. Forming a bit line by etching a portion of the polysilicon layer by an etching process using a bit line mask, forming a third insulating layer on the entire structure, and then etching using a storage electrode contact hole mask. Etching the third insulating film and the second insulating film, and etching the exposed semiconductor substrate to a predetermined depth. Forming holes and drains, and forming a storage electrode by etching a predetermined portion of the polysilicon in an etching process using a storage electrode mask by applying a polysilicon film doped with a second conductive impurity on the entire structure; And diffusing the doped impurities in the bit line and the storage electrode to the exposed semiconductor substrate by a heat treatment process to form LDD structures of the source and the drain, respectively. 제1항에 있어서, 상기 제1절연막 스페이서의 두께와, 비트라인과 저장전극용 다결정실리콘에 포함되는 두께와 포함되는 불순물의 양을 조절하여 소오스와 드레인 접합이 얕은 접합 LDD로 형성되도록 하는 것을 특징으로 하는 모스 전계 효과 트랜지스터의 제조 방법.The source and drain junctions of claim 1, wherein the source and drain junctions are formed of a shallow junction LDD by controlling a thickness of the first insulating layer spacer, a thickness included in the bit line and the polycrystalline silicon for the storage electrode, and an amount of impurities. The manufacturing method of the MOS field effect transistor. 제1항에 있어서, 상기 제1절연막 스페이서는 상기 제2절연막을 식각하는 공정에서 식각장벽 역할을 하는 물질인 것을 특징으로 하는 모스 전계 효과 트랜지스터의 제조 방법.The method of claim 1, wherein the first insulating layer spacer is a material that serves as an etching barrier in the process of etching the second insulating layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950017497A 1995-06-26 1995-06-26 Manufacturing Method of Semiconductor Device KR970003984A (en)

Priority Applications (1)

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KR1019950017497A KR970003984A (en) 1995-06-26 1995-06-26 Manufacturing Method of Semiconductor Device

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KR1019950017497A KR970003984A (en) 1995-06-26 1995-06-26 Manufacturing Method of Semiconductor Device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100454628B1 (en) * 1997-06-24 2005-01-05 주식회사 하이닉스반도체 Method for forming wordline strapping of semiconductor device to improve photolithography process margin and area of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100454628B1 (en) * 1997-06-24 2005-01-05 주식회사 하이닉스반도체 Method for forming wordline strapping of semiconductor device to improve photolithography process margin and area of semiconductor device

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