KR970003596A - Method of forming fine pattern of semiconductor device - Google Patents

Method of forming fine pattern of semiconductor device Download PDF

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Publication number
KR970003596A
KR970003596A KR1019950015020A KR19950015020A KR970003596A KR 970003596 A KR970003596 A KR 970003596A KR 1019950015020 A KR1019950015020 A KR 1019950015020A KR 19950015020 A KR19950015020 A KR 19950015020A KR 970003596 A KR970003596 A KR 970003596A
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KR
South Korea
Prior art keywords
material layer
pattern
etching process
semiconductor device
photoresist pattern
Prior art date
Application number
KR1019950015020A
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Korean (ko)
Inventor
김승준
신기수
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950015020A priority Critical patent/KR970003596A/en
Publication of KR970003596A publication Critical patent/KR970003596A/en

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Abstract

본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로, 반도체기판 상부에 절연막 및 물질층을 순차적으로 형성하고 상기 물질층 상부에 마스크를 이용하여 감광막패턴을 형성한 다음, 상기 감광막패턴을 마스크로하여 CD가 크게 형성된 부분을 주로하여 상대적으로 빠른 식각속도를 갖고 등방성식각한 다음, 상기 CD가 작게 형성된 부분을 주로하여 이방성식각공정을 실시하여 상기 감광막패턴의 CD와 관계없이 하부의 물질층을 같은 CD를 갖도록 식각함으로써 같은 크기의 물질층패턴을 형성하고 반도체소자의 특성을 유지하여 반도체소자의 신뢰성을 향상시킬 수 있는 기술이다.The present invention relates to a method for forming a fine pattern of a semiconductor device, wherein an insulating film and a material layer are sequentially formed on a semiconductor substrate, and a photoresist pattern is formed on the material layer by using a mask, and then the photoresist pattern is used as a mask. After isotropic etching with a relatively fast etching speed mainly on the portion where the CD is formed large, and then performing anisotropic etching process on the portion where the CD is formed small, the lower material layer is the same as the CD of the photoresist pattern. By etching to have a material layer pattern of the same size and maintaining the characteristics of the semiconductor device is a technology that can improve the reliability of the semiconductor device.

Description

반도체 소자의 미세패턴 형성방법Method of forming fine pattern of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1C도는 본 발명의 실시예에 따른 반도체소자의 미세패턴 형성공정을 도시한 단면도.1C is a cross-sectional view illustrating a process of forming a fine pattern of a semiconductor device according to an embodiment of the present invention.

Claims (6)

반도체기판의 셀부와 주변회로부에 CD 차이를 갖는 감광막패턴이 리소그래피공정으로 형성되고, 상기 감광막패턴을 이용한 식각공정으로 상기 감광막패턴 하부의 물질층을 같은 크기의 CD로 미세패턴을 형성하는 반도체소자의 미세패턴 형성방법에 있어서, 상기 반도체기판 상부에 절연막, 물질층 및 감광막패턴을 순차적으로 형성하는 공정과, 상기 감광막패턴을 마스크로 하여 상기 물질층을 등방성식각하는 공정과, 상기 감광막패턴을 마스크로 하여 상기 물질층의 남아있는 부분을 이방성식각하여 물질층패턴을 형성하는 공정을 포함하는 반도체소자의 미세패턴 형성방법.A photosensitive film pattern having a CD difference between a cell portion and a peripheral circuit portion of a semiconductor substrate is formed by a lithography process, and an etching process using the photosensitive film pattern forms a fine pattern of a material layer under the photosensitive film pattern with a CD having the same size. A method of forming a fine pattern, comprising: sequentially forming an insulating film, a material layer, and a photoresist pattern on an upper surface of the semiconductor substrate, isotropically etching the material layer using the photoresist pattern as a mask, and using the photoresist pattern as a mask And anisotropically etching the remaining portion of the material layer to form a material layer pattern. 제1항에 있어서, 상기 등방성식각공정은 식각실을 압력을 500 내지 230mTorr로 하여 실시되는 것을 특징으로 하는 반도체소자의 미세패턴 형성방법.The method of claim 1, wherein the isotropic etching process is performed using a pressure of 500 to 230 mTorr in the etching chamber. 제1항에 있어서, 상기 등방성식각공정은 CF4 가스가 사용되는 것을 특징으로 하는 반도체소자의 미세패턴 형성방법.The method of claim 1, wherein the isotropic etching process uses CF4 gas. 제1항에 있어서, 상기 등방성식각공정의 등방성식각정도는 2 내지 25%인 것을 특징으로 하는 반도체소자의 미세패턴 형성방법.The method of claim 1, wherein the isotropic etching degree of the isotropic etching process is 2 to 25%. 제1항에 있어서, 상기 등방성식각공정은 상기 셀부에서 상기 주변회로부의 10 내지 80% 속도로 실시되는 것을 특징으로 하는 반도체소자의 미세패턴 형성방법.The method of claim 1, wherein the isotropic etching process is performed at the cell portion at a speed of 10 to 80% of the peripheral circuit portion. 제1항에 있어서, 상기 이방성식각공정은 C12 가스가 사용되는 것을 특징으로 하는 반도체소자의 미세패턴 형성방법.The method of claim 1, wherein the anisotropic etching process uses C12 gas. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950015020A 1995-06-08 1995-06-08 Method of forming fine pattern of semiconductor device KR970003596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950015020A KR970003596A (en) 1995-06-08 1995-06-08 Method of forming fine pattern of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950015020A KR970003596A (en) 1995-06-08 1995-06-08 Method of forming fine pattern of semiconductor device

Publications (1)

Publication Number Publication Date
KR970003596A true KR970003596A (en) 1997-01-28

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KR1019950015020A KR970003596A (en) 1995-06-08 1995-06-08 Method of forming fine pattern of semiconductor device

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KR (1) KR970003596A (en)

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