KR970018081A - Contact hole formation method of semiconductor device - Google Patents

Contact hole formation method of semiconductor device Download PDF

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Publication number
KR970018081A
KR970018081A KR1019950033162A KR19950033162A KR970018081A KR 970018081 A KR970018081 A KR 970018081A KR 1019950033162 A KR1019950033162 A KR 1019950033162A KR 19950033162 A KR19950033162 A KR 19950033162A KR 970018081 A KR970018081 A KR 970018081A
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KR
South Korea
Prior art keywords
forming
oxide film
etching
contact hole
film
Prior art date
Application number
KR1019950033162A
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Korean (ko)
Inventor
김진웅
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950033162A priority Critical patent/KR970018081A/en
Publication of KR970018081A publication Critical patent/KR970018081A/en

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Abstract

본 발명은 반도체소자의 콘택홀 형성방법에 관한 것으로, 반도체기판 상부에 물질층패턴을 형성하고 전체표면상부를 평탄화시키는 제1산화막을 형성한 다음, 상기 제2산화막 상부에 일정두께 질화막을 형성하고 콘택마스크를 이용한 식각공정으로 상기 질화막고 일정두께의 제1산화막을 식각한 다음, 전체표면상부에 일정두께 제2산화막을 형성하고 이를 이방성식각하여 제2산화막 스페이서를 형성한 다음, 상기 질화막과 제2산화막 스페이서를 마스크로하여 과도식각함으로써 상기 반도체기판의 예정된 부분을 노출시키는 콘택홀을 형성하여 타층의 손상없이 예정된 부분에 예정된 크기의 콘택홀을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a contact hole in a semiconductor device, comprising forming a material layer pattern on a semiconductor substrate and forming a first oxide film to planarize an entire surface thereof, and then forming a nitride film having a predetermined thickness on the second oxide film. After etching the nitride film and the first oxide film having a predetermined thickness by an etching process using a contact mask, a second oxide film having a predetermined thickness is formed on the entire surface and anisotropically etched to form a second oxide spacer, and then the nitride film and the By over-etching with a double oxide spacer as a mask to form a contact hole exposing a predetermined portion of the semiconductor substrate to form a contact hole of a predetermined size in the predetermined portion without damaging other layers to improve the characteristics and reliability of the semiconductor device It is a technology that enables high integration.

Description

반도체소자의 콘택홀 형성방법Contact hole formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 실시예에 따른 반도체소자의 콘택홀 형성공정을 도시한 단면도.2A to 2D are cross-sectional views showing a contact hole forming process of a semiconductor device according to an embodiment of the present invention.

Claims (3)

반도체기판 상부에 물질층패턴을 형성하는 공정과, 전체표면상부를 평탄화시키는 제1산화막을 형성하는 공정과, 상기 제1산화막 상부에 질화막을 일정두께 형성하는 공정과, 콘택마스크를 이용한 식각공정으로 상기 질화막을 부분식각하고 연속적으로 상기 제1산화막을 일정깊이 식각하는 공정과, 진체표면상부에 제2산화막을 일정두께 형성하는 공정과, 상기 제1산화막의 식각면에 제2산화막 스페이서를 형성하는 공정과, 상기 질화막과 제2산화막 스페이서를 마스크로하여 과도식각함으로써 상기 반도체기판의 예정된 부분을 노출시키는 콘택홀을 형성하는 공정을 포함하는 반도체소자의 콘택홀 형성방법.Forming a material layer pattern on the semiconductor substrate, forming a first oxide film to planarize the entire upper surface, forming a nitride film on the first oxide film by a predetermined thickness, and etching using a contact mask. Partially etching the nitride film and continuously etching the first oxide film in a predetermined depth, forming a second oxide film at a predetermined thickness on the solid surface, and forming a second oxide spacer on the etching surface of the first oxide film. And forming a contact hole exposing a predetermined portion of the semiconductor substrate by overetching the nitride film and the second oxide film spacer as a mask. 제1항에 있어서, 상기 질화막은 100 내지 500Å의 두께로 형성되는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.The method of claim 1, wherein the nitride layer is formed to a thickness of about 100 to about 500 microns. 제1항에 있어서, 상기 콘택마스크를 이용한 식각공정은 상기 제1산화막과 질화막의 식각선택비를 1 : 10이상으로 하여 실시되는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.The method of claim 1, wherein the etching process using the contact mask is performed using an etching selectivity ratio of the first oxide film and the nitride film to be greater than or equal to 1: 10. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950033162A 1995-09-29 1995-09-29 Contact hole formation method of semiconductor device KR970018081A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950033162A KR970018081A (en) 1995-09-29 1995-09-29 Contact hole formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950033162A KR970018081A (en) 1995-09-29 1995-09-29 Contact hole formation method of semiconductor device

Publications (1)

Publication Number Publication Date
KR970018081A true KR970018081A (en) 1997-04-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950033162A KR970018081A (en) 1995-09-29 1995-09-29 Contact hole formation method of semiconductor device

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KR (1) KR970018081A (en)

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