KR960702942A - 반도체 장치에 대한 평탄화 에칭백의 허용공차한계, 신뢰도 및 안정성 개선방법(method enhancing planarization etchback margin, reliability, and stability of a semiconductor device) - Google Patents

반도체 장치에 대한 평탄화 에칭백의 허용공차한계, 신뢰도 및 안정성 개선방법(method enhancing planarization etchback margin, reliability, and stability of a semiconductor device)

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Publication number
KR960702942A
KR960702942A KR1019950705472A KR19950705472A KR960702942A KR 960702942 A KR960702942 A KR 960702942A KR 1019950705472 A KR1019950705472 A KR 1019950705472A KR 19950705472 A KR19950705472 A KR 19950705472A KR 960702942 A KR960702942 A KR 960702942A
Authority
KR
South Korea
Prior art keywords
margin
reliability
stability
semiconductor device
method enhancing
Prior art date
Application number
KR1019950705472A
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR960702942A publication Critical patent/KR960702942A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material
KR1019950705472A 1993-06-04 1995-12-04 반도체 장치에 대한 평탄화 에칭백의 허용공차한계, 신뢰도 및 안정성 개선방법(method enhancing planarization etchback margin, reliability, and stability of a semiconductor device) KR960702942A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/072,279 US5403780A (en) 1993-06-04 1993-06-04 Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device
PCT/US1994/005628 WO1994029899A1 (en) 1993-06-04 1994-05-19 Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device

Publications (1)

Publication Number Publication Date
KR960702942A true KR960702942A (ko) 1996-05-23

Family

ID=22106632

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950705472A KR960702942A (ko) 1993-06-04 1995-12-04 반도체 장치에 대한 평탄화 에칭백의 허용공차한계, 신뢰도 및 안정성 개선방법(method enhancing planarization etchback margin, reliability, and stability of a semiconductor device)

Country Status (4)

Country Link
US (1) US5403780A (ko)
JP (1) JPH09501543A (ko)
KR (1) KR960702942A (ko)
WO (1) WO1994029899A1 (ko)

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US5763937A (en) * 1990-03-05 1998-06-09 Vlsi Technology, Inc. Device reliability of MOS devices using silicon rich plasma oxide films
JP2640174B2 (ja) * 1990-10-30 1997-08-13 三菱電機株式会社 半導体装置およびその製造方法
JP2809018B2 (ja) * 1992-11-26 1998-10-08 日本電気株式会社 半導体装置およびその製造方法
US5503882A (en) * 1994-04-18 1996-04-02 Advanced Micro Devices, Inc. Method for planarizing an integrated circuit topography
US5516729A (en) * 1994-06-03 1996-05-14 Advanced Micro Devices, Inc. Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate
EP0703611B1 (en) * 1994-08-31 2007-05-02 Texas Instruments Incorporated Method for insulating metal leads using a low dielectric constant material, and structures formed therewith
KR0159016B1 (ko) * 1995-06-28 1999-02-01 김주용 반도체소자의 금속배선간 절연막의 제조방법
US5556806A (en) * 1995-06-28 1996-09-17 Taiwan Semiconductor Manufacturing Company Spin-on-glass nonetchback planarization process using oxygen plasma treatment
US6191484B1 (en) 1995-07-28 2001-02-20 Stmicroelectronics, Inc. Method of forming planarized multilevel metallization in an integrated circuit
US5637190A (en) * 1995-09-15 1997-06-10 Vanguard International Semiconductor Corporation Plasma purge method for plasma process particle control
US5665644A (en) * 1995-11-03 1997-09-09 Micron Technology, Inc. Semiconductor processing method of forming electrically conductive interconnect lines and integrated circuitry
US5893750A (en) * 1995-11-13 1999-04-13 Advanced Micro Devices, Inc. Method for forming a highly planarized interlevel dielectric structure
KR970052338A (ko) * 1995-12-23 1997-07-29 김주용 반도체 소자의 제조방법
US5821163A (en) * 1996-02-13 1998-10-13 Vlsi Technology, Inc. Method for achieving accurate SOG etchback selectivity
US5700741A (en) * 1996-05-20 1997-12-23 Vanguard International Semiconductor Corporation Plasma purge method for plasma process particle control
US5783481A (en) * 1996-06-05 1998-07-21 Advanced Micro Devices, Inc. Semiconductor interlevel dielectric having a polymide for producing air gaps
US6599847B1 (en) * 1996-08-27 2003-07-29 Taiwan Semiconductor Manufacturing Company Sandwich composite dielectric layer yielding improved integrated circuit device reliability
JPH1092810A (ja) * 1996-09-10 1998-04-10 Mitsubishi Electric Corp 半導体装置
TW408192B (en) * 1996-10-02 2000-10-11 Winbond Electronics Corp Method for forming a film over a spin-on-glass layer by means of plasma-enhanced chemical-vapor deposition
US5854503A (en) * 1996-11-19 1998-12-29 Integrated Device Technology, Inc. Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit
KR100230405B1 (ko) 1997-01-30 1999-11-15 윤종용 반도체장치의 다층 배선 형성방법
TW331021B (en) * 1997-04-29 1998-05-01 United Microelectronics Corp Manufacturing method of utilizing chemical mechanical polishing planarization pre-metal dielectric
US6057227A (en) * 1997-06-23 2000-05-02 Vlsi Technology, Inc. Oxide etch stop techniques for uniform damascene trench depth
US6265315B1 (en) * 1998-06-24 2001-07-24 Taiwan Semiconductor Manufacturing Company Method for improving chemical/mechanical polish uniformity over rough topography for semiconductor integrated circuits
KR100480230B1 (ko) * 1998-08-05 2005-07-05 주식회사 하이닉스반도체 반도체장치의금속배선형성방법
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
US6140240A (en) * 1999-01-07 2000-10-31 Vanguard International Semiconductor Corporation Method for eliminating CMP induced microscratches
US6503818B1 (en) 1999-04-02 2003-01-07 Taiwan Semiconductor Manufacturing Company Delamination resistant multi-layer composite dielectric layer employing low dielectric constant dielectric material
US6130149A (en) * 1999-08-16 2000-10-10 Taiwan Semiconductor Manufacturing Company Approach for aluminum bump process
US6916736B2 (en) * 2002-03-20 2005-07-12 Macronix International Co., Ltd. Method of forming an intermetal dielectric layer
JP2005203619A (ja) * 2004-01-16 2005-07-28 Sharp Corp 層間絶縁膜の形成方法
US7119312B2 (en) * 2004-07-09 2006-10-10 Sedlmayr Steven R Microwave fluid heating and distillation method
US20060237802A1 (en) * 2005-04-21 2006-10-26 Macronix International Co., Ltd. Method for improving SOG process

Family Cites Families (6)

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Publication number Priority date Publication date Assignee Title
DE3881032T2 (de) * 1988-05-26 1993-11-25 Fairchild Semiconductor Verbindungssystem von hoher Leistungsfähigkeit für eine integrierte Schaltung.
US4986878A (en) * 1988-07-19 1991-01-22 Cypress Semiconductor Corp. Process for improved planarization of the passivation layers for semiconductor devices
US5128279A (en) * 1990-03-05 1992-07-07 Vlsi Technology, Inc. Charge neutralization using silicon-enriched oxide layer
US5003062A (en) * 1990-04-19 1991-03-26 Taiwan Semiconductor Manufacturing Co. Semiconductor planarization process for submicron devices
US5252515A (en) * 1991-08-12 1993-10-12 Taiwan Semiconductor Manufacturing Company Method for field inversion free multiple layer metallurgy VLSI processing
JPH06149482A (ja) * 1992-11-11 1994-05-27 Hitachi Ltd 外部記憶装置

Also Published As

Publication number Publication date
US5403780A (en) 1995-04-04
JPH09501543A (ja) 1997-02-10
WO1994029899A1 (en) 1994-12-22

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