KR960043135A - 성형된 캡슐화 전자 구성요소 및 그의 제조 방법 - Google Patents
성형된 캡슐화 전자 구성요소 및 그의 제조 방법 Download PDFInfo
- Publication number
- KR960043135A KR960043135A KR1019960013807A KR19960013807A KR960043135A KR 960043135 A KR960043135 A KR 960043135A KR 1019960013807 A KR1019960013807 A KR 1019960013807A KR 19960013807 A KR19960013807 A KR 19960013807A KR 960043135 A KR960043135 A KR 960043135A
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- South Korea
- Prior art keywords
- integrated circuit
- interconnect
- electrically conductive
- elastomer
- molded
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract 11
- 239000010703 silicon Substances 0.000 claims abstract 11
- 229920001971 elastomer Polymers 0.000 claims description 8
- 239000000806 elastomer Substances 0.000 claims description 8
- 239000004033 plastic Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 claims 6
- 239000002991 molded plastic Substances 0.000 claims 6
- 229920002379 silicone rubber Polymers 0.000 claims 3
- 229920001187 thermosetting polymer Polymers 0.000 claims 2
- 238000005538 encapsulation Methods 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000002245 particle Substances 0.000 claims 1
- 238000003825 pressing Methods 0.000 claims 1
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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Abstract
본 발명은 실리콘 디바이스, 칩, 혹은 집적 회로를 포함하는 성형된 캡슐화 전자 구성요소는, 제조가 용이하고 파손 및 전위의 가능성이 최소화되는 것을 특징으로 하며, 실리콘 집적 회로가 위치되고, 완전한 밀봉 플라스틱내에 장착된 압축되는 얇은 탄성중합체성의 이방성 전기전도성의 유연한 상호연결부를 가진 리드 프레임을 포함한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 리드 프레임, 탄성중합체, 집적 회로, 및 캡슐화 플라스틱의 특정 관계를 도시하는, 본 발명에 따라 제조된 성형된 캡슐화 전자 구성요소의 단면을 개략적으로 도시하는 단면도.
Claims (9)
- 집적 회로(an integrated circuit)가 장착되는 리드 프레임(a lead frame)을 포함하는 성형된 캡슐화 전자 구성요소 (a molded encapsulated electronic component)를 제조하는 방법에 있어서, 상기 방법은 : 상부 및 하부 금형을 갖는 밀봉된 금형 공동(an enveloping mold cavity)의 상기 하부 금형에 상기 리드 프레임을 유지 시키는 단계와; 상기 리드 프레임과 접촉하는 제1면과 제2면을 갖는 얇은 탄성중합체성의 이방성 전기전도성의 유연한 상호연결부를 상기 리드 프레임상에 배치하는 단계와; 상기 상호연결부의 상기 제2면상에 제1면 및 제2면을 갖는 집적 회로의 상기 제1면을 배치하는 단계와; 상기 하부 금형상에 상기집적 회로의 상기 제2면을수납하기에 적합한 공동 벽(cavity wall)을 갖는 밀봉된 상부 금형(enclosing upper mold half)을 위치시키고(상기 집적 회로의 상기 제2면은 상기 상부 금형의 상기 공동 벽과 동일한 평면내에 존재한다), 상기 상부 금형을 상기 집적 회로 및 상기 탄성중합체성의 이방성 전기전도성의 유연한 상호연결부에 대해 가압시켜 상기 상호연결부를 압축시키고, 상기 집적 회로를 상기 밀봉된 금형내의 사전결정된 위치에 유지시키는 단계와; 전단-박만 열경화성 플라스틱(shear-thinning thermosetting plastic)을 상기금형 공동의 내부로 도입하는 단계와; 상기 전단-박만 열경화성 플라스틱을 경화시킴으로써 상기 집적 회로상에 장착된 상기 얇고 압축된 탄성중합체성의 이방성 전기전도성의 유연한 상호연결부를 가진 상기 리드 프레임을 포함하는 성형된 전자 구성요소를 형성시키는 단계; 및 상기 집적 회로상에 장착된 상기 얇고 압축된 탄성중합체성의 이방성 전기전도성의 유연한 상호연결부를 구비한 상기 리드 프레임을 포함하는 상기 성형된 전자 구송요소를 회수하는 단계를 포함하는 성형된 캡슐화 전자 구성요소의 제조 방법.
- 제1항에 있어서, 상기 얇은 탄성중합체성의 이방성 전기전도성의 유연한 상호연결부가 실리콘 탄성중합체인 성형된 캡슐화 전가 구성요소의 제조 방법.
- 제1항에 있어서, 상기 얇은 탄성중합체성의 이방성 전기전도성의 유연한 상호연결부가 상기 상호연결부의 상기 제1 및 제2면을 전기적으로 접속시키는 원주형상의 배열로 어레이된 다수의 전도성 입자를 함유하는 실리콘 탄성중합체인 성형된 캡슐화 전자 구성요소의 제조 방법.
- 제1항에 있어서, 상기 얇은 탄성중합체성의 이방성 전기전도성의 유연한 상호연결부가상기 상호연결부의 상기 제1 및 제2면을 접속시키는 전도성 실리콘 탄성중합체의 층과 비전도성 실리콘 탄성중합체의 층을 교대로 형성시킨 성형된 캡슐화 전자 구성요소의 제조 방법.
- 제1항에 있어서, 상기 얇은 탄성중합체성의 이방성 전기전도성의 유연한 상호연결부가 비전도성 실리콘층과 상기 상호연결부의 상기 제1 및 제2면을 접속시키는 전도성 금속층을 교대로 형성시킨 성형된 캡슐화 전자 구성요소의 제조 방법.
- 제1항에 있어서, 상기 집적 회로가 실리콘 칩인 성형된 캡슐화 전자 구성요소의 제조 방법.
- 적어도 하나가 리드 프레임의 중앙부로부터 연장되는 상기 리드 프레임의 에지 근처에서 끝이나는 다수의 리드를 포함하는 리드 프레임과; 제1면에서 제2면까지 두께를 가로질러 연장하는 다수의 개별적인 전기전도성 경로를 포함하는 얇은 탄성중합체성의 이방성 전기전도성의 유연한 상호연결부(상기 상호연결부의 상기 제1면은 상기 리드 프레임의 상기 중앙부에 인접한 리드와 전기적으로 접촉되어 있고, 상기 유연한 상호연결부 탄성중합체는 그의 압축되지 않은 두께보다 얇은 두께까지 압축되어 있다)와; 상기 탄성중합체상에 장착된 제1 및 제2면을 갖는 집적 회로로서, 상기 실리콘 직접 회로의 상기 제1면은 상기 탄성중합체의 상기 제2면과 전기 적으로 접촉되어 있고, 상기 집적 회로는 상기 집적 회로의 상기 제2면을 제외하고 상기 캡슐화 전가 구성요소 내에 밀봉되어 있는, 상기 실리콘 집적 회로와; 상기 제1 및 제2면을 갖는 성형된 플라스틱 몸체로서, 노출되고 상기 플라스틱 몸체의 상기 제2면과 동일한 평면내에 있는 상기 집적 회로의 상기 제2면을 제외하고 상기 전자 구성요소를 감싸고 있는 상기 성형된 플라스틱 몸체를 포함하는 성형된 캡슐화 전자 구성요소.
- 리드 프레임의 주축을 따라 상기 리드 프레임의 중앙부로부터 각각 연장되어 제1 및 제2횡방향 에지의 근처에서 각각 끝이 나는 제1 및 제2다수의 리드를 포함하는 리드프레임과; 제1면에서 제2면까지 두께를 가로질러 연장하는 다수의 개별적이고 전기전도성 경로를 포함하는 얇은 탄성중합체성의 이방성 전기전도성의 유연한 상호연결부(상기 상호연결부의 상기 제1면은 상기 리드 프레임과 전기적으로 접촉되어 있고, 상기 경로중 적어도 하나는 상기 리드 프레임상의 리드와 전기적으로 접촉하며, 상기 유연한 상호연결부 탄성중합체는 그의압축되지 않은 두께보다 얇은 두께까지 압축되어 있다)와; 상기 탄성중합체상에 장착되고 상기 탄성중합체를압축하는 제1 및 제2면을 갖는 실리콘 집적 회로로서, 상기 실리콘 집적 회로의 제1면은 상기 상호연결부의상기 제2면과 접촉되어 있고, 상기 집적 회로는 상기 집적회로의 상기 제2면을 제외하고 상기 캡슐화 전자구성요소내에 밀봉되어 있는 상기 실리콘 집적 회로와; 상기 제1 및 제2면을 갖는 성형된 플라스틱 몸체로서, 노출되고 상기 플라스틱 몸체의 상기 제2면과 동일한 평면내에 있는 상기 실리콘 집적 회로의 상기 제1면을제외하고 상기 전자 구성요소를 감싸고 있는 상기 성형된 플라스틱 몸체를 포함하는 성형된 캡슐화 전자 구성요소.
- 제7항에 있어서, 상기 집적 회로가 실리콘 칩인 성형된 캡슐화 전자 구성요소.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US43159095A | 1995-05-01 | 1995-05-01 | |
US08/431,590 | 1995-05-01 |
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KR960043135A true KR960043135A (ko) | 1996-12-23 |
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Application Number | Title | Priority Date | Filing Date |
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KR1019960013807A KR960043135A (ko) | 1995-05-01 | 1996-04-30 | 성형된 캡슐화 전자 구성요소 및 그의 제조 방법 |
Country Status (3)
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US (1) | US5773322A (ko) |
JP (1) | JP3361689B2 (ko) |
KR (1) | KR960043135A (ko) |
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US6080605A (en) * | 1998-10-06 | 2000-06-27 | Tessera, Inc. | Methods of encapsulating a semiconductor chip using a settable encapsulant |
US6740960B1 (en) | 1997-10-31 | 2004-05-25 | Micron Technology, Inc. | Semiconductor package including flex circuit, interconnects and dense array external contacts |
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US6838760B1 (en) * | 2000-08-28 | 2005-01-04 | Micron Technology, Inc. | Packaged microelectronic devices with interconnecting units |
DE10058622A1 (de) * | 2000-11-15 | 2002-05-29 | Vishay Semiconductor Gmbh | Gemouldetes elektronisches Bauelement |
DE10058608A1 (de) | 2000-11-25 | 2002-05-29 | Vishay Semiconductor Gmbh | Leiterstreifenanordnung für ein gemouldetes elektronisches Bauelement und Verfahren zum Moulden |
EP1220309A1 (en) * | 2000-12-28 | 2002-07-03 | STMicroelectronics S.r.l. | Manufacturing method of an electronic device package |
US6748650B2 (en) * | 2001-06-27 | 2004-06-15 | Visteon Global Technologies, Inc. | Method for making a circuit assembly having an integral frame |
US6818155B2 (en) * | 2002-01-02 | 2004-11-16 | Intel Corporation | Attaching components to a printed circuit card |
US20060261498A1 (en) * | 2005-05-17 | 2006-11-23 | Micron Technology, Inc. | Methods and apparatuses for encapsulating microelectronic devices |
TW200739758A (en) * | 2005-12-09 | 2007-10-16 | Fairchild Semiconductor Corporaton | Device and method for assembling a top and bottom exposed packaged semiconductor |
US7833456B2 (en) * | 2007-02-23 | 2010-11-16 | Micron Technology, Inc. | Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece |
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US4419640A (en) * | 1979-12-17 | 1983-12-06 | Omron Tateisi Electronics Co. | Unitary contact-terminal blades integrally formed in a molded base |
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JPH0737159Y2 (ja) * | 1990-04-26 | 1995-08-23 | ホシデン株式会社 | メモリカードコネクタ |
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1996
- 1996-04-30 KR KR1019960013807A patent/KR960043135A/ko not_active Application Discontinuation
- 1996-05-01 JP JP11073696A patent/JP3361689B2/ja not_active Expired - Fee Related
-
1997
- 1997-06-27 US US08/884,095 patent/US5773322A/en not_active Expired - Lifetime
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Publication number | Publication date |
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US5773322A (en) | 1998-06-30 |
JP3361689B2 (ja) | 2003-01-07 |
JPH08306720A (ja) | 1996-11-22 |
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